Multi-addressable register files and format conversions associated therewith

Patent metadata

Field	Value
Publication number	US-9411585-B2
Application number	US-201113234520-A
Country	US
Kind code	B2
Filing date	Sep 16, 2011
Priority date	Sep 16, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

First claim

What is claimed is:

1. A computer program product for executing a machine instruction, said computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one field used to specify a first register;
at least one other field used to specify a second register; and
at least one opcode field including an operation code to identify a format conversion instruction, wherein the operation code explicitly specifies a format of information in the first register and a format of information to be placed in the second register; and

executing, by the processor, the machine instruction, the executing comprising:
obtaining from the first register a single-precision binary floating point datum in a first representation in a first format;
converting the single-precision binary floating point datum of the first representation in the first format to a converted single-precision binary floating point datum of a second representation in a second format,

wherein the first format is of a different size than the second format and
wherein at least one of the first format or the second format is 64-bit; and
placing the converted single-precision binary floating point datum in the second register, wherein the single-precision binary floating point datum obtained from the first register comprises a signaling Not-a-Number (SNaN) as defined by a standard for representing the floating point datum, and wherein the SNaN is preserved as a SNaN in the second register.

2. The computer program product of claim 1 , wherein the method further comprises:
determining that the single-precision binary floating point datum of the first representation in the first format is to be converted to a single-precision binary floating point datum of the second representation in the second format; and
obtaining the format conversion instruction, based on the determining.

3. The computer program product of claim 2 , wherein the determining is performed by a compiler executing on the processor or on another processor.

4. The computer program product of claim 1 , wherein at least one of the first register and the second register is a register of a multi-addressable register file.

5. The computer program product of claim 4 , wherein the multi-addressable register file comprises a plurality of registers, and wherein a first subrange of bits of one or more registers of the plurality of registers is defined for data of a first format, a second subrange of bits of the one or more registers of the plurality of registers is defined for data of one or more second formats, and an entire range of bits of the one or more registers of the plurality of registers is defined for data of a third format.

6. The computer program product of claim 5 , wherein each of the plurality of registers is defined to include 64-bit scalar single-precision floating point data and 32-bit vector single-precision floating point data.

7. The computer program product of claim 1 , wherein the machine instruction is inserted between a first instruction and a second instruction, the second instruction having a dependence on the first instruction, and the first instruction to produce data having a different format than a format used by the second instruction.

8. The computer program product of claim 7 , wherein the first register includes a datum of the first instruction to be converted.

9. The computer program product of claim 1 , wherein (i) the first representation comprises a vector representation and the first format is 32-bit and the second representation comprises a scalar representation and the second format is 64-bit, or (ii) the first representation comprises a scalar representation and the first format is 64-bit and the second representation comprises a vector representation and the second format is 32-bit.

10. The computer program product of claim 1 , wherein the format conversion instruction includes a replication function.

11. A computer system for executing a machine instruction, said computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining, by the processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one field used to specify a first register;
at least one other field used to specify a second register; and
at least one opcode field including an operation code to identify a format conversion instruction, wherein the operation code explicitly specifies a format of information in the first register and a format of information to be placed in the second register; and

executing, by the processor, the machine instruction, the executing comprising:
obtaining from the first register a single-precision binary floating point datum in a first representation in a first format;
converting the single-precision binary floating point datum of the first representation in the first format to a converted single-precision binary floating point datum of a second representation in a second format, wherein the first format is of a different size than the second format and wherein at least one of the first format or the second format is 64-bit; and
placing the converted single-precision binary floating point datum in the second register, wherein the single-precision binary floating point datum obtained from the first register comprises a signaling Not-a-Number (SNaN) as defined by a standard for representing the floating point datum, and wherein the SNaN is preserved as a SNaN in the second register.

12. The computer system of claim 11 , wherein the method further comprises:
determining that the single-precision binary floating point datum of the first representation in the first format is to be converted to a single-precision binary floating point datum of the second representation in the second format; and
obtaining the format conversion instruction, based on the determining.

13. The computer system of claim 11 , wherein at least one of the first register and the second register is a register of a multi-addressable register file, and wherein the multi-addressable register file comprises a plurality of registers, and wherein a first subrange of bits of one or more registers of the plurality of registers is defined for data of a first format, a second subrange of bits of the one or more registers of the plurality of registers is defined for data of one or more second formats, and an entire range of bits of the one or more registers of the plurality of registers is defined for data of a third format.

14. The computer system of claim 13 , wherein each of the plurality of registers is defined to include 64-bit scalar single-precision floating point data and 32-bit vector single-precision floating point data.

15. The computer system of claim 11 , wherein the machine instruction is inserted between a first instruction and a second instruction, the second instruction having a dependence on the first instruction, and the first instruction to produce data having a different format than a format used by the second instruction.

16. The computer system of claim

Assignees

• Gschwind Michael K
• Olsson Brett
• IBM

Inventors

• Gschwind Michael K
• Olsson Brett

Classifications

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30025 Primary

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30014

  with variable precision · CPC title