Vector instruction for presenting complex conjugates of respective complex numbers

Patent metadata

Field	Value
Publication number	US-9411583-B2
Application number	US-201113977614-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An apparatus is described having a semiconductor chip that has an instruction execution pipeline. The instruction execution pipeline has an execution unit with logic circuitry to perform the following for an instruction: accept input vector elements representing real and imaginary parts of a plurality of complex numbers; and, present the complex conjugates of the complex numbers.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor chip having an instruction execution pipeline, said instruction execution pipeline having an execution unit to perform the following for an instruction:
accept input vector elements representing real and imaginary parts of a plurality of complex numbers; and
present complex conjugates of said complex numbers, wherein the execution unit supports presenting the complex conjugates for a plurality of input vector formats that differ as to which input vector elements correspond to real parts and which input vector elements correspond to imaginary parts.

2. The apparatus of claim 1 wherein said execution unit includes write mask circuitry.

3. The apparatus of claim 1 wherein the complex conjugates are not rounded.

4. The apparatus of claim 1 wherein said instruction has a format that specifies through an immediate operand which input vector format applies.

5. The apparatus of claim 1 wherein said execution unit supports presenting the complex conjugates in a plurality of output vector formats that differ as to which output vector elements correspond to real parts and which output vector elements correspond to imaginary parts.

6. The apparatus of claim 1 wherein said execution unit is to permute said input vector elements.

7. A method comprising:
performing the following by executing an instruction with an execution unit:
accepting input vector elements representing real and imaginary parts of a plurality of complex numbers; and
creating complex conjugates of said complex numbers, wherein the execution unit supports presenting the complex conjugates for a plurality of input vector formats that differ as to which input vector elements correspond to real parts and which input vector elements correspond to imaginary parts.

8. The method of claim 7 further comprising applying a write mask to said complex conjugates.

9. The method of claim 7 wherein the complex conjugates are not rounded.

10. The method of claim 7 wherein said instruction has a format that specifies through an immediate operand which input vector format applies.

11. The method of claim 7 wherein said execution unit supports presenting the complex conjugates in a plurality of output vector formats that differ as to which output vector elements correspond to real parts and which output vector elements correspond to imaginary parts.

12. The method of claim 7 wherein said creating includes permuting said input vector elements.

13. An apparatus comprising:
a semiconductor chip having an instruction execution pipeline, said instruction execution pipeline having an execution unit to perform the following for an instruction:
accept input vector elements representing real and imaginary parts of a plurality of complex numbers, said input vector elements within a single input vector provided from a single vector register; and
present complex conjugates of said complex numbers, wherein the execution unit supports presenting the complex conjugates for a plurality of input vector formats that differ as to which input vector elements correspond to real parts and which input vector elements correspond to imaginary parts.

14. The apparatus of claim 13 wherein said execution unit includes write mask circuitry.

15. The apparatus of claim 13 wherein the complex conjugates are not rounded.

16. The apparatus of claim 13 wherein said instruction has a format that specifies through an immediate operand which input vector format applies.

17. The apparatus of claim 13 wherein said execution unit supports presenting the complex conjugates in a plurality of output vector formats that differ as to which output vector elements correspond to real parts and which output vector elements correspond to imaginary parts.

18. The apparatus of claim 13 wherein said execution unit is to permute said input vector elements.

19. The apparatus of claim 1 wherein said instruction has a format that specifies through an opcode which input vector format applies.

20. The apparatus of claim 13 wherein said instruction has a format that specifies through an opcode which input vector format applies.

Assignees

• Sair Suleyman
• Ould-Ahmed-Vall Elmoustapha
• Intel Corp

Inventors

• Sair Suleyman
• Ould-Ahmed-Vall Elmoustapha

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F17/5022

  Physics · mapped topic

• G06F9/30038

  using a mask · CPC title