Implementing enhanced performance flash memory devices

Patent metadata

Field	Value
Publication number	US-9411519-B2
Application number	US-201514695828-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Dec 16, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A method and apparatus for implementing performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement. The system includes an on-flash chip memory buffer buffering garbage collection and scrub requests. Garbage collection and scrub operations are interleaved with mainline reads and writes.

First claim

What is claimed is:

1. A method for implementing enhanced performance in a flash memory system comprising:
configuring an internal bus in the flash memory device for data movement;
configuring a memory buffer in the flash memory device for buffering garbage collection and scrub requests from a flash controller or a host controller;
configuring a function engine in the flash memory device for performing garbage collection and scrub operations using the internal bus for data movement, preserving input/output (I/O) bandwidth and interleaving garbage collection and scrub operations with mainline reads and writes.

2. The method as recited in claim 1 wherein configuring said internal bus in the flash memory device for data movement includes configuring a switching infrastructure multiplexer within the flash memory device for selecting between the internal bus and a mainline bus.

3. The method as recited in claim 2 wherein configuring said function engine in the flash memory device for performing garbage collection and scrub operations using the internal bus for data movement includes configuring a multiplexer control and a command decoder with said function engine for performing garbage collection and scrub operations using the internal bus for data movement.

4. The method as recited in claim 1 wherein configuring said function engine in the flash memory device for performing garbage collection and scrub operations using the internal bus for data movement includes said function engine taking control of said internal bus and said function engine taking control of each block to be erased for performing an erase operation.

5. The method as recited in claim 1 wherein configuring said function engine in the flash memory device for performing garbage collection and scrub operations using the internal bus for data movement includes said function engine taking control of said internal bus and said function engine taking control of each block to be scrubbed for performing a scrub operation.

6. The method as recited in claim 1 includes configuring a controller coupled to the flash memory device to communicate a list of blocks to the flash memory device for garbage collection, and initiating a background garbage collection process at the flash memory device.

7. The method as recited in claim 6 includes providing an order of write operations and background process erase operations for garbage collection in parallel to current writes in a write queue to free blocks in the flash memory device to accommodate upcoming writes.

8. The method as recited in claim 1 includes connecting blocks to a mainline bus by default for write operations.

9. The method as recited in claim 1 includes configuring a controller coupled to the flash memory device to communicate a list of blocks to the flash memory device to be scrubbed and initiating a scrub process at the flash memory device.

Assignees

• IBM

Inventors

• Tressler Gary A
• Vidyapoornachary Diyanesh Babu C

Classifications

• G06F3/0652 Primary

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0607

  Interleaved addressing · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0261

  using reference counting · CPC title