Resist hardening and development processes for semiconductor device manufacturing

Patent metadata

Field	Value
Publication number	US-9411237-B2
Application number	US-201414205324-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 14, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

First claim

The invention claimed is:

1. A method of forming an etch mask on a substrate, the method comprising:
forming a resist layer on a substrate;
exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions;
performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber and vibrating the substrate during at least a portion of the hardening process; and
dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer.

2. The method of claim 1 wherein the first regions are exposed regions of the resist layer and the second regions are non-exposed regions of the resist layer.

3. The method of claim 1 wherein the first regions are non-exposed regions of the resist layer and the second regions are exposed regions of the resist layer.

4. The method of claim 1 wherein forming the resist layer includes coating the substrate with a photoresist layer having bonds that are broken when exposed to at least one of ultra-violet light, extreme-ultra-violet light and an electron beam.

5. The method of claim 1 wherein exposing one or more regions of the resist layer comprises:
placing a mask proximate the resist layer; and
exposing the resist layer to an energy source through the mask.

6. The method of claim 1 wherein performing the hardening process comprises:
loading the substrate into an ALD chamber; and
exposing the substrate to a metal precursor within the ALD chamber to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer.

7. The method of claim 6 wherein the etch resistance of the first regions of the resist layer are increased at both a surface and a bulk region of the resist layer.

8. The method of claim 6 wherein exposing the substrate to the metal precursor includes forming metal oxide within the first regions of the resist layer.

9. The method of claim 1 wherein performing the hardening process includes irradiating the substrate with ultraviolet light during at least a portion of the hardening process.

10. The method of claim 1 wherein dry etching the resist layer includes performing reactive ion etching on the resist layer.

11. The method of claim 1 further comprising etching the substrate using the patterned resist layer as an etch mask.

12. The method of claim 11 wherein dry etching the resist layer and etching the substrate are performed in the same etch chamber.

13. A method of patterning a substrate, the method comprising:
forming a resist layer on a substrate;
exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions;
developing the resist layer to pattern the resist layer; and
performing a hardening process on the patterned resist layer to increase the etch resistance of the patterned resist layer, the hardening process including exposing the patterned resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber and vibrating the substrate during at least a portion of the hardening process.

14. The method of claim 13 wherein exposed regions of the resist layer are removed during development.

15. The method of claim 13 wherein non-exposed regions of the resist layer are removed during development.

16. The method of claim 13 wherein developing the resist layer includes exposing the resist layer to a wet developer.

17. The method of claim 13 wherein forming the resist layer includes coating the substrate with a photoresist layer having bonds that are broken when exposed to at least one of ultra-violet light, extreme-ultra-violet light and an electron beam.

18. The method of claim 13 wherein performing the hardening process comprises:
loading the substrate into an ALD chamber; and
exposing the substrate to a metal precursor within the ALD chamber to increase the etch resistance of the resist layer.

Assignees

• Applied Materials Inc

Inventors

• Xie Peng
• Bencher Christopher Dennis
• Dai Huixiong
• Michaelson Timothy
• Deshmukh Subhash

Classifications

• H10P72/7602

  the wafers being placed on a robot blade or gripped by a gripper for conveyance · CPC title

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• H10P72/0421 Primary

  for drying etching · CPC title

• G03F7/405 Primary

  Treatment with inorganic or organometallic reagents after imagewise removal · CPC title