System and method for statistical post-silicon validation

Patent metadata

Field	Value
Publication number	US-9411007-B2
Application number	US-201213663258-A
Country	US
Kind code	B2
Filing date	Oct 29, 2012
Priority date	Oct 29, 2012
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

The system and method described herein relate to a bug positioning system for post-silicon validation of a prototype integrated circuit using statistical analysis. Specifically, the bug positioning system samples output and intermediate signals from a prototype chip to generate signatures. Signatures are grouped into passing and failing groups, modeled, and compared to identify patterns of acceptable behavior and unacceptable behavior and locate bugs in space and time.

First claim

What is claimed:

1. A post-silicon validation method for debugging a semiconductor device with one or more observable connections, the method comprising:
testing, by one or more processors, the semiconductor device over a plurality of time intervals, wherein the testing is associated with an expected test outcome and causes the semiconductor device to produce an actual output and one or more signals, wherein each signal is associated with an observable connection;
logging, by one or more processors, a group of signatures for the signals;
dividing, by one or more processors, the group of signatures into a passing group having passing group signature values if the actual output conforms with the expected test outcome or a failing group having failing group signature values if the actual output does not conform with the expected test outcome;
determining, by one or more processors, a model of signal behavior for each of the one or more signals by (i) calculating a passing group mean signature value from each of the passing group signature values tested during the same time interval to form a passing group band centered about the mean passing group signature values over each of the plurality of time intervals and bounded by a threshold passing range, and (ii) calculating a failing group mean signature value from each of the failing group signature values tested during the same time interval to form a failing group band centered about the mean failing group signature values over each of the plurality of time intervals and bounded by a threshold failing range; and
identifying, by one or more processors, (i) the signals associated with a divergence of the failing group band from the passing group band, wherein the divergence occurs when any portion of the failing group band threshold failing range is no longer within the threshold passing range, and (ii) a time interval from among the plurality of time intervals associated with the divergence.

2. The method of claim 1 , further comprising:
locating a bug in the semiconductor device using the divergence and the one or more observable connections to which the signals associated with the divergence are associated.

3. The method of claim 1 , wherein:
the act of testing includes repeating one or more testing operations during each of the plurality of time intervals, and
the act of logging includes logging a signature for each signal for each time interval from among the plurality of time intervals,
the method further comprising:
receiving a window length parameter specifying a number of cycles in each time interval from among the plurality of time intervals.

4. The method of claim 1 , wherein the passing group and the failing group of signature values have statistically significant separation.

5. The method of claim 1 , wherein the group of signatures is based on one or more of a signal toggle counting scheme, a signal time at one counting scheme, a signal at zero counting scheme, a cyclic redundancy check, hamming distance, or a hashing function.

6. The method of claim 1 , wherein the threshold passing range comprises:
the mean passing group signature values plus or minus a multiple of the standard deviation, and
wherein the threshold failing range comprises:
the mean failing group signature values plus or minus a multiple of the standard deviation.

7. The method of claim 1 , wherein identifying the signals associated with the divergence comprises:
identifying a bug band characterized by the magnitude of the divergence between the passing group band and the failing group band for each signal; and
ranking the signals according to the magnitude of the bug band of each signal.

8. The method of claim 7 , further comprising:
receiving a bug band threshold parameter, and
wherein identifying the signals associated with the divergence further comprises:
comparing the bug band of each signal to the bug band threshold parameter; and
identifying signals for which the magnitude of the bug band exceeds the bug band threshold parameter.

9. The method of claim 1 , wherein dividing the group of signatures includes setting aside a portion of the passing group into a training group, and
wherein the model of signal behavior includes the passing group band, a training group band, and the failing group band, the method further comprising:
identifying, as noisy signals, one or more signals where the passing group band diverges from the training group band; and
revising the model of signal behavior by excluding from the model one or more signatures associated with the noisy signals.

10. A post-silicon validation system for debugging a semiconductor device coupled to the system, the system comprising:
a processor for executing computer-readable instructions;
a memory storing computer-readable instructions that when executed by the processor cause the post-silicon validation system to:
test the semiconductor device over a plurality of time intervals, wherein the test is associated with an expected test outcome and causes the semiconductor device to produce an actual output and one or more signals, wherein each signal is associated with an observable connection;
log a group of signatures for the signals;
divide the group of signatures into a passing group having passing group signature values if the actual output conforms with the expected test outcome or a failing group having failing group signature values if the actual output does not conform with the expected test outcome;
determine a model of signal behavior for each of the one or more signals by (i) calculating a passing group mean signature value from each of the passing group signature values tested during the same time interval to form a passing group band centered about the mean passing group signature values over each of the plurality of time intervals and bounded by a threshold passing range, and (ii) calculating a failing group mean signature value from each of the failing group signature values tested during the same time interval to form a failing group band centered about the mean failing group signature values over each of the plurality of time intervals and bounded by a threshold failing range; and
identifying (i) the signals associated with a divergence of the failing group band from the passing group band, wherein the divergence occurs when any portion of the failing group band threshold failing range is no longer within the threshold passing range, and (ii) a time interval from among the plurality of time intervals associated with the divergence.

11. The post-silicon validation system of claim 10 , wherein the memory further includes instructions that when executed by the processor cause the post-silicon validation system to locate a bug in the semiconductor device using the divergence and the one or more observable connections to which the signals associated with the divergence are associated.

12. The post-silicon validation system of claim 10 , wherein the instructions that when executed by the processor cause the post-silicon validation system to test the semiconductor device include instructions to repeat one or more testing operations during each of the plurality of time intervals,
wherein the instructions that when executed by the processor cause the post-silicon validation system to log a group of signatures include instructions to log a signature for each signal for each time interval from among the plurality of time intervals, and
wherein the memory further includes instructions that when executed by the processor cause the post-silicon validation system to receive a window length parameter specifying a number of cycles in each time interval from a

Assignees

• Univ Michigan Regents

Inventors

• Bertacco Valeria
• Deorio Andrew
• Khudia Daya Shanker

Classifications

• G01R29/26

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title

• G01R31/3183

  Generation of test inputs, e.g. test vectors, patterns or sequences · CPC title

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title