High voltage polymer dielectric capacitor isolation device

Patent metadata

Field	Value
Publication number	US-9408302-B2
Application number	US-201514643230-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Aug 6, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

First claim

What is claimed is:

1. An isolation device, comprising:
a pre-metal dielectric (PMD) layer disposed over a substrate;
a first metal level disposed over the PMD layer;
a dielectric layer disposed over the first metal layer;
a second metal level disposed over the dielectric layer;
a polymer dielectric layer disposed over the second metal level, the polymer dielectric layer comprising primarily a layer of polymer selected from the group consisting of polyimide and poly(p-phenylene-2,6-benzobisoxazole) (PBO), said polymer being at least 20 microns thick;
a third metal level disposed over said polymer dielectric layer, said third metal level extending into upper via holes in said polymer dielectric layer to form upper vias which make electrical connections to said second metal level;
bondpads disposed over said third metal level; and
a dielectric overcoat dielectric layer disposed over said third metal level, said dielectric overcoat dielectric layer exposing said bondpads;
said isolation device containing a plurality of isolation components selected from the group consisting of a capacitor and a transformer, said isolation components being formed in at least said second metal level and said third metal level.

2. The isolation device of claim 1 , wherein:
each instance of said isolation components is a capacitor;
a lower plate of said capacitor is provided in said second metal level;
an upper plate of said capacitor is provided in said third metal level;
said lower plate is electrically coupled to a first instance of said bondpads through an instance of said upper vias;
said upper plate is electrically coupled to a second instance of said bondpads.

3. The isolation device of claim 2 , wherein said dielectric layer is at least 5 microns thick.

4. The isolation device of claim 1 , wherein:
each instance of said isolation components is a transformer;
a lower winding of said transformer is provided in said second metal level;
an upper winding of said transformer is provided in said third metal level;
said lower winding is electrically coupled to a first two instances of said bondpads through instances of said upper vias;
said upper plate is electrically coupled to a second two instances of said bondpads.

5. The isolation device of claim 1 , in which said second metal layer has a sheet resistance less than 10 milliohms/square, and said third metal layer has a sheet resistance less than 10 milliohms/square.

6. The isolation device of claim 1 , in which said layer of polymer in said polymer dielectric layer is polyimide.

7. The isolation device of claim 1 , in which said layer of polymer in said polymer dielectric layer is PBO.

8. The isolation device of claim 1 , in which each of said isolation components is operable to 400 volts continuous operation, and able to withstand a voltage transient up to 5000 root-mean-square (rms) volts and a voltage surge up 10000 volts.

9. The isolation device of claim 1 , in which said substrate is single crystal silicon.

10. The isolation device of claim 1 , in which said second metal level includes a layer of copper 4 to 6 microns thick, and said third metal level includes a layer of copper 4 to 6 microns thick.

Assignees

• Texas Instruments Inc

Inventors

• Bonifield Thomas Dyer
• Williams Byron
• Jaganathan Shrinivasan
• Larkin David
• Saraiya Dhaval Atul

Classifications

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title