Video processor with reduced memory bandwidth and methods for use therewith

Patent metadata

Field	Value
Publication number	US-9407920-B2
Application number	US-201314133775-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Jan 22, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

First claim

What is claimed is:

1. A video processing device comprising:
a video processing unit that decodes an enhanced bit depth video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data;
a tile engine that includes:
a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units that each include pixel data from at least a portion of a corresponding row of a video frame; and
a tile compression/decompression module, coupled to the tile accumulation module, that reduces memory bandwidth requirements by generating and storing compressed video frame data in a compressed video frame buffer, wherein the tile compression/decompression module is configured to compress the plurality of video span units into a plurality of compressed video span units individually by applying data object compression to the pixel data from the at least the portion of the corresponding row of the video frame, to store the plurality of compressed video span units in the compressed video frame buffer, and further to retrieve the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

2. The video processing device of claim 1 further comprising:
a span engine, coupled to the tile engine and the compressed video frame buffer, that includes at least one register that defines a range of memory addresses corresponding to the compressed video frame buffer.

3. The video processing device of claim 2 further comprising:
a graphics processing unit that processes at least one graphical plane of the video frame, based on uncompressed graphical frame data; and
wherein the span engine further includes a span compression/decompression module that generates compressed graphical frame data for storage in a compressed graphical frame buffer by compressing the uncompressed graphical frame data into a plurality of compressed graphical span units and further that retrieves the compressed graphical frame data from the compressed graphical frame buffer by retrieving the plurality of compressed graphical span units and generating the uncompressed graphical frame data by decompressing the plurality of compressed graphical span units.

4. The video processing device of claim 3 wherein the at least one register defines a range of memory addresses corresponding to the compressed graphical frame buffer.

5. The video processing device of claim 4 wherein the span engine identifies a write command from the graphics processing unit as corresponding to the compressed graphical frame buffer when a memory address corresponding to the write command falls within the range of memory addresses corresponding to the compressed graphical frame buffer; and
wherein the span engine identifies a read command from the graphics processing unit as corresponding to the compressed graphical frame buffer when a memory address corresponding to the read command falls within the range of memory addresses corresponding to the compressed graphical frame buffer.

6. The video processing device of claim 4 further comprising:
a display processing unit, coupled to the span engine, that processes the video frame and at least one graphical plane of the video frame, based on the uncompressed video frame data and the uncompressed graphical frame data;
wherein the span compression/decompression module retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

7. The video processing device of claim 6 wherein the span engine further includes a cache for storing the uncompressed graphical frame data;
wherein the span engine responds to requests from the graphics processing unit and the display processing unit by retrieving selected ones of the uncompressed graphical frame data from the cache when the selected ones of the uncompressed graphical frame data are stored in the cache and that further retrieves the selected ones of the uncompressed graphical frame data from the compressed graphical frame buffer when the selected ones of the uncompressed graphical frame data are not stored in the cache.

8. The video processing device of claim 7 wherein the span engine responds to requests from the display processing unit by retrieving selected ones of the uncompressed video frame data from the cache when the selected ones of the uncompressed video frame data are stored in the cache and that further retrieves the selected ones of the uncompressed video frame data from the compressed video frame buffer by retrieving the corresponding one of the plurality of compressed video span units and generating the selected ones of the uncompressed video frame data by decompressing the corresponding one of the plurality of compressed video span units when the selected ones of the uncompressed video frame data are not stored in the cache.

9. The video processing device of claim 1 wherein the compressed video frame buffer stores the compressed video frame data corresponding to an entire frame of the video input signal, and wherein the video processing unit issues a read command to the compressed video frame buffer for at least a portion of a video frame and receives a corresponding portion of the uncompressed video frame data from the compressed video frame buffer in response to the read command.

10. The video processing device of claim 1 wherein the video processing unit transcodes the enhanced bit depth video input signal into a processed video signal by re-encoding the decoded video signal.

11. A method for processing an enhanced bit depth video input signal into a processed video signal, the method comprising:
decoding the enhanced bit depth video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data;
accumulating the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units that each include pixel data from at least a portion of a corresponding row of a video frame;
reducing memory bandwidth requirements by generating compressed video frame data for storage in a compressed video frame buffer, wherein generating the compressed video frame data includes compressing the plurality of video span units into a plurality of compressed video span units individually by applying data object compression to the pixel data from the at least the portion of the corresponding row of the video frame; and
retrieving the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

12. The method of claim 11 further comprising:
storing a range of memory addresses corresponding to the compressed video frame buffer in a register.

13. The method of claim 12 further comprising:
processing at least one graphical plane of the video frame, based on uncompressed graphical frame data;
generating compressed graphical frame data for storage in a compressed graphical frame buffer by compressing the uncompressed graphical frame data into a plurality of compressed graphical span units; and

Assignees

• Vixs Systems Inc

Inventors

• Guo Xin
• Yang Qi
• Hong Edward
• Cheung Wendy Wai Yin
• Young Eric
• Yeh Chun-Chin

Classifications

• G09G2360/128

  Frame memory using a Synchronous Dynamic RAM [SDRAM] · CPC title

• H04N19/426

  using memory downsizing methods · CPC title

• H04N19/40

  using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream · CPC title

• H04N19/17

  the unit being an image region, e.g. an object · CPC title

• H04N19/15 Primary

  by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer · CPC title