Pulse width modulation data recovery device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9407479-B2
Application number	US-201514710713-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	Jul 14, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.

First claim

What is claimed is:

1. A pulse width modulation (PWM) data recovery device, comprising:
a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal comprising a differential positive data signal and a differential negative data signal;
a PWM data processing logic circuit; and
an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data to the PWM data processing logic circuit,
wherein a reference clock is received by the alignment buffer and the PWM data processing logic circuit, and the symbol data is transmitted from the alignment buffer to the PWM data processing logic circuit in synchronization with the reference clock.

2. The PWM data recovery device of claim 1 , wherein a phase of the differential positive data signal and a phase of the differential negative data signal are opposite to each other.

3. The PWM data recovery device of claim 2 , wherein the alignment buffer is configured to store the PWM bit in units of bits in synchronization with the differential positive data signal or the differential negative data signal, and transmit the symbol data in units of symbols in synchronization with the reference clock.

4. The PWM data recovery device of claim 2 , wherein the DTS circuit is configured to delay one of the differential positive data signal and the differential negative data signal.

5. The PWM data recovery device of claim 1 , wherein the PWM bit is one of a plurality of PWM bits, and the alignment buffer is configured to compare the synch pattern with the PWM bits received from the DTS circuit and activate the bit lock signal according to a result of the comparison of the synch pattern with the PWM bits.

6. The PWM data recovery device of claim 1 , wherein the DTS circuit comprises a decoder configured to generate the PWM bit using the differential data signal, and the decoder is an integrator-type decoder or an oversampling-type decoder.

7. The PWM data recovery device of claim 1 , wherein the reference clock is a phase locked loop (PLL) reference clock.

8. A method of driving a pulse width modulation (PWM) data recovery device, comprising:
generating a PWM bit using a differential data signal;
activating a bit lock signal, by an alignment buffer, by detecting a synch pattern;
recovering symbol data by receiving the PWM bit in synchronization with the differential data signal in response to the bit lock signal being activated; and
transmitting the symbol data from the alignment buffer to a PWM data processing logic circuit,
wherein a reference clock is received by the alignment buffer and the PWM data processing logic circuit, and the symbol data is transmitted from the alignment buffer to the PWM data processing logic circuit in synchronization with the reference clock.

9. The method of claim 8 , wherein the differential data signal comprises a differential positive data signal and a differential negative data signal, and a phase of the differential positive data signal and a phase of the differential negative data signal are opposite to each other.

10. The method of claim 9 , wherein recovering the symbol data comprises storing the PWM bit in units of bits in synchronization with the differential positive data signal or the differential negative data signal.

11. The method of claim 9 , further comprising:
delaying one of the differential positive data signal and the differential negative data signal.

12. The method of claim 8 , wherein the symbol data is transmitted in units of symbols.

13. The method of claim 8 , wherein activating the bit lock signal comprises:
comparing the synch pattern with a plurality of PWM bits, wherein the PWM bit is one of the plurality of PWM bits; and
activating the bit lock signal according to a result of the comparison of the synch pattern with the PWM bits.

14. The method of claim 8 , wherein the reference clock is a phase locked loop (PLL) reference clock.

15. A system-on-chip (SoC), comprising:
a modulator-demodulator (MODEM) comprising a first physical layer, wherein the first physical layer comprises a first low speed unit and a first high speed unit; and
an application processor (AP) comprising a second physical layer, wherein the second physical layer comprises a second low speed unit and a second high speed unit,
wherein the MODEM and the AP communicate with each other through the first and second physical layers, and each of the first and second low speed units comprises a pulse width modulation (PWM) data recovery device, comprising:
a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal comprising a differential positive data signal and a differential negative data signal;
a PWM data processing logic circuit; and
an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data to the PWM data processing logic circuit,
wherein a reference clock is received by the alignment buffer and the PWM data processing logic circuit, and the symbol data is transmitted from the alignment buffer to the PWM data processing logic circuit in synchronization with the reference clock.

16. The SoC of claim 15 , wherein a phase of the differential positive data signal and a phase of the differential negative data signal are opposite to each other.

17. The SoC of claim 16 , wherein the DTS circuit is configured to delay one of the differential positive data signal and the differential negative data signal.

18. The SoC of claim 15 , wherein the DTS circuit comprises:
a decoder configured to generate the PWM bit using the differential data signal, wherein the decoder is an integrator-type decoder or an oversampling-type decoder.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee June-Hee
• Bae Jun-Han
• Kim Bong-Kyu
• Ruy Jong-Jae

Classifications

• H04L25/4902 Primary

  Pulse width modulation; Pulse position modulation · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title