Receiving stage and method for receiving

Patent metadata

Field	Value
Publication number	US-9407228-B2
Application number	US-201414477825-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Mar 6, 2012
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A receiver stage for receiving a receive signal comprises M receiving paths, each receiving path comprises a signal processor and K comparators. The signal processors of the M receiving paths are configured to generate, for each of the M receiving paths, an amplified version of the receive signal, such that an amplification gain of the respective receiving path increases from a first of the M receiving paths to a last of the M receiving paths. For each of the M receiving paths the K comparators of the respective receiving paths are configured to compare the amplified receive signal of the respective receiving path with a respective threshold value. For each of the M receiving paths the threshold value increases from a first of the K comparators to the last of the K comparators.

First claim

The invention claimed is:

1. Receiving stage for receiving a radio frequency signal, comprising:
M receiving paths, each receiving path comprising a signal processor and K comparators,
wherein the signal processors of the M receiving paths are configured to generate, for each of the M receiving paths, an amplified version of the radio frequency signal such that an amplification gain of the respective receiving path increases from a first of the M receiving paths to a last of the M receiving paths,
wherein for each of the M receiving paths the K comparators of the respective receiving paths are configured to compare the amplified radio frequency signal of the respective receiving path with a respective threshold value, and for each of the M receiving paths the threshold value increases from a first of the K comparators to the last of the K comparators.

2. Receiving stage according to claim 1 , wherein the M receiving paths are arranged in parallel and coupled to a common node at its input side.

3. Receiving stage according to claim 2 , wherein the respective signal processors of the M receiving paths comprise different gains.

4. Receiving stage according to claim 1 , wherein each signal processor of the M receiving paths comprises an amplifier.

5. Receiving stage according to claim 4 , wherein each signal processor of the M receiving paths comprises a demodulator arranged between the respective amplifier and the K comparators.

6. Receiving stage according to claim 5 , wherein the demodulator comprises a peak detector, power detector, envelope detector and/or a detector for demodulating an amplitude modulator signal.

7. Receiving stage according to claim 1 , wherein the signal processors of the M receiving paths are arranged in series and wherein the K comparators of the M receiving paths are arranged in parallel.

8. Receiving stage according to claim 7 , wherein each signal processor of the M receiving paths comprises an amplifier and wherein the gains of the respective amplifiers of the M receiving paths are equal so that at least the amplification gain of the last of the M receiving paths is based on a combination of the gain of the amplifier of the first of the M receiving paths and the gain of the amplifier of the last of the M receiving paths.

9. Receiving stage according to claim 8 , wherein each signal processor of the M receiving paths comprises an amplifier and a demodulator arranged between the amplifier and the K comparators, wherein for each of the M receiving paths a tapping for the next of the M receiving paths is arranged between the respective amplifier and the respective demodulator.

10. Receiving stage according to claim 1 , wherein the K comparators are arranged in parallel and coupled to the respective signal processor via a common node.

11. Receiving stage according to claim 1 , wherein each of the K comparators is coupled to a correlator unit configured to detect a bit sequence forwarded by the respective comparator.

12. Receiving stage according to claim 11 , wherein the K comparators are configured to forward the amplified radio frequency signal, if the amplified radio frequency signal is above a respective threshold value and if a difference between the amplified radio frequency signal and an interfering signal is larger than an average distance of the K threshold values, wherein the radio frequency signal comprises the interfering signal and a data signal carrying the bit sequence.

13. Receiving stage according to claim 11 , wherein the respective correlator comprises an XNOR-operator unit or XOR-operator unit.

14. Receiving stage according to claim 11 , wherein each correlator of the M receiving path is coupled to a digital selector configured to output information based on the bit sequence detected by one of the K correlators.

15. Receiving stage according to claim 14 , wherein the digital selector comprises a combinational logic for selecting and/or processing one or more of M×K channels, each channel is formed by the respective correlator of the M receiving path.

16. Receiving stage according to claim 14 , wherein the digital selector is configured to output information on the respective correlator in which the bit sequence is detected.

17. Receiving stage according to claim 1 , wherein the M−1 differences between two successive amplification gains of the M amplification gains are equidistant.

18. Receiving stage according to claim 17 , wherein an average distance between the K threshold values is at least two times smaller than the difference between two successive amplification gains.

19. Receiving stage according to claim 1 , wherein each receiving path comprises a plurality of K comparators which are arranged in parallel and coupled to the respective signal processor via a common node.

20. Receiving stage according to claim 1 , wherein the radio frequency signal comprises a bit sequence.

21. Receiving stage according to claim 1 , wherein the receiving stage comprises at least three receiving paths.

22. Method for receiving a radio frequency signal, using a receiving stage comprising M receiving paths, each receiving path comprises a signal processor and K comparators, the method comprising:
generating an amplified version of the radio frequency signal for each of the M receiving paths, using the respective signal processor of the average receiving path, such that an amplification gain of the respective receiving paths increases from a first of the averaging path to a last of the receiving paths; and
comparing the amplified radio frequency signal of the respective receiving paths with a respective threshold value for each of the M receiving paths, using the K comparators of the respective receiving paths, wherein for each of the receiving paths the threshold value increases from a first of the K comparators to a last of the K comparators.

Assignees

• Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E V

Inventors

• Oehler Frank
• Eppel Markus
• Milosiu Heinrich

Classifications

• H04L25/08

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title

• H03G3/3052 Primary

  in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver (H03G3/32, H03G3/34 take precedence) · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title