Differential amplifier circuit

Patent metadata

Field	Value
Publication number	US-9407221-B2
Application number	US-201414528196-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Nov 13, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.

First claim

The invention claimed is:

1. A differential amplifier circuit, comprising:
a first input terminal;
a second input terminal;
a first transistor having a control terminal connected to the first input terminal;
a second transistor having a control terminal connected to the second input terminal;
a third transistor having a control terminal applied predetermined bias voltage;
a current source connected to a first terminal of each of the first transistor, the second transistor, and the third transistor;
a first output terminal connected to a second terminal of the first transistor;
a second output terminal connected to a second terminal of the second transistor;
a first passive element connected between the first input terminal and the first output terminal;
a second passive element connected between the second input terminal and the second output terminal; and
a load circuit connected to the second terminal of each of the first transistor and the second transistor;
wherein the load circuit is a current mirror circuit configured to copy current flowing in the third transistor and apply the current to the first transistor and the second transistor.

2. A differential amplifier circuit, comprising:
a first input terminal;
a second input terminal;
a first transistor having a control terminal connected to the first input terminal;
a second transistor having a control terminal connected to the second input terminal;
a third transistor having a control terminal applied predetermined bias voltage;
a current source connected to a first terminal of each of the first transistor, the second transistor, and the third transistor;
a first output terminal connected to a second terminal of the first transistor;
a second output terminal connected to a second terminal of the second transistor;
a first passive element connected between the first input terminal and the first output terminal;
a second passive element connected between the second input terminal and the second output terminal;
a first non-inverting output circuit provided between the second terminal of the first transistor and the first output terminal; and
a second non-inverting output circuit provided between the second terminal of the second transistor and the second output terminal.

3. The differential amplifier circuit according to claim 2 , wherein the first non-inverting output circuit and the second non-inverting output circuit are source follower circuits.

4. The differential amplifier circuit according to claim 2 , comprising a load circuit connected to the second terminal of each of the first transistor and the second transistor.

5. The differential amplifier circuit according to claim 4 , wherein the load circuit is a current mirror circuit configured to copy current flowing in the third transistor and apply the current to the first transistor and the second transistor.

6. The differential amplifier circuit according claim 1 , wherein a device size of the third transistor is smaller than the device size of the first transistor and the second transistor.

7. The differential amplifier circuit according to claim 1 , wherein
the control terminal is a gate terminal or a base terminal,
the first terminal is a source terminal or an emitter terminal, and
the second terminal is a drain terminal or a collector terminal.

Assignees

• Toshiba Kk

Inventors

• Itakura Tetsuro
• Furuta Masanori
• Kimura Shunsuke
• Kawata Go
• Funaki Hideyuki

Classifications

• H03F2203/45101

  Control of the DC level being present · CPC title

• H03F3/45654

  Controlling the active amplifying circuit of the differential amplifier · CPC title

• H03F2203/45512

  the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title

• H03F3/45183 Primary

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title