Harmonics cancellation circuit for a power amplifier

Patent metadata

Field	Value
Publication number	US-9407209-B2
Application number	US-201414566505-A
Country	US
Kind code	B2
Filing date	Dec 10, 2014
Priority date	Dec 10, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.

First claim

The invention claimed is:

1. A circuit comprising:
an input port for applying a sinusoidal input signal;
a first buffering means for converting the sinusoidal input signal into a square wave signal, wherein the square wave signal has a DC level defined by an adjustable threshold voltage level;
an output port for outputting the square wave signal to a power amplifier; and
a feedback loop comprising:
a low pass filtering means arranged for filtering the square wave signal, and
comparing means arranged for comparing the DC level of a filtered signal received from the low pass filtering means with a pre-set reference level, wherein the reference level is selected for cancelling a given harmonic component, and the comparing means further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.

2. The circuit as in claim 1 , further comprising a second buffering means arranged for buffering the square wave signal received from the first buffering means and for outputting the buffered square wave signal via the output port.

3. The circuit as in claim 1 , having a single-ended topology.

4. The circuit as in claim 1 , wherein the given harmonic component is an even order harmonic frequency.

5. The circuit as in claim 2 , wherein the first and second buffering means are connected in series.

6. The circuit as in claim 1 , wherein the first buffering means includes a first transistor and a second transistor coupled to form an inverter circuit, and a third transistor and a fourth transistor coupled to the inverter circuit.

7. The circuit as in claim 6 , wherein the third transistor connects the inverter circuit to a first power rail, and the fourth transistor connects the inverter circuit to a second power rail.

8. The circuit as in claim 1 , wherein the low pass filtering means includes a first-order RC filter.

9. A circuit comprising:
an input port configured to receive a sinusoidal input signal;
a first buffer circuit configured to convert the sinusoidal input signal into a square wave signal, wherein the square wave signal has a DC level defined by an adjustable threshold voltage level;
an output port configured to provide the square wave signal to a power amplifier; and
a feedback loop comprising:
a low pass filter circuit configured to receive the square wave signal, and
a comparator component configured to compare an output from the low pass filter circuit with a reference signal, wherein the reference signal is adapted to cancel a given harmonic component, wherein the comparator component is further configured to provide a correction signal to the first buffer circuit in order to adjust the threshold voltage level of the first buffer circuit.

10. The circuit as in claim 9 , further comprising a second buffer circuit configured to buffer the square wave signal from the first buffer circuit, and to provide a buffered square wave signal via the output port.

11. The circuit as in claim 10 , wherein the first and second buffer circuits are connected in series.

12. The circuit as in claim 9 , having a single-ended topology.

13. The circuit as in claim 9 , wherein the given harmonic component is an even order harmonic frequency.

14. The circuit as in claim 9 , wherein the first buffer circuit includes a first transistor and a second transistor coupled to form an inverter circuit, and a third transistor and a fourth transistor coupled to the inverter circuit.

15. The circuit as in claim 14 , wherein the third transistor connects the inverter circuit to a first power rail, and the fourth transistor connects the inverter circuit to a second power rail.

16. The circuit as in claim 1 , wherein the low pass filter includes a first-order RC filter.

Assignees

• Stichting Imec Nederland

Inventors

• Ba Ao

Classifications

• H03F1/0233 Primary

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F3/217 Primary

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/165

  A filter circuit coupled to the input of an amplifier · CPC title