Phased array architecture configured for current reuse

Patent metadata

Field	Value
Publication number	US-9407206-B2
Application number	US-201213454667-A
Country	US
Kind code	B2
Filing date	Apr 24, 2012
Priority date	Apr 24, 2012
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A phased array architecture configured for current reuse is disclosed. In an exemplary embodiment, an apparatus includes a current mode phase rotator (PR) module configured to generate phase shifted in-phase (I) and quadrature-phase (Q) current signals, and a current mode residual sideband (RSB) correction module configured to correct residual sideband error associated with the phase shifted I and Q current signals. The RSB correction module and the PR module form a phased array element configured to reuse a DC supply current.

First claim

What is claimed is:

1. An apparatus comprising:
a current mode phase rotator (PR) module configured to generate phase shifted in-phase (I) and quadrature-phase (Q) current signals; and
a current mode residual sideband (RSB) correction module configured to correct residual sideband error associated with the phase shifted I and Q current signals, the RSB correction module and the PR module are stacked to use a same current flow from a single connection to a power supply.

2. The apparatus of claim 1 , further comprising a gm block configured to generate I and Q current signals that are input to the PR module, the gm block further stacked to use the same current flow from the single connection to the power supply.

3. The apparatus of claim 1 , the RSB correction module configured to perform residual sideband correction based on RSB control signals to generate RSB corrected I and Q current signals.

4. The apparatus of claim 3 , the RSB correction module comprising at least one transistor bank connected to each of the phase shifted I and Q current signals, respectively, the at least one transistor bank configured to generate the RSB corrected I and Q current signals based on RSB control signals.

5. The apparatus of claim 1 , the PR module configured to provide a phase shift based on phase control signals to generate the phase shifted I and Q current signals.

6. The apparatus of claim 5 , the PR module comprising a plurality of transistors configured to provide the phase shift based on four phase control signals, and wherein activation of each phase control signal results in a selected phase shift.

7. The apparatus of claim 1 , further comprising at least one filter stage coupled to the PR module.

8. The apparatus of claim 1 , the RSB correction module coupled to a mixer that upconverts the RSB corrected I and Q signals in a phased array transmitter.

9. The apparatus of claim 1 , the RSB correction module coupled to a mixer that downconverts received I and Q signals in a phased array receiver.

10. The apparatus of claim 1 , the PR module and the RSB correction module form an array element, the apparatus comprising:
a plurality of the array elements forming a phased array transmitter, the plurality of array elements configured to transmit I and Q signals.

11. The apparatus of claim 1 , the PR module and the RSB correction module form an array element, the apparatus comprising:
a plurality of array elements forming a phased array receiver, the plurality of array elements configured to receive I and Q signals.

12. The apparatus of claim 1 , further comprising a DC offset correction module connected to the PR module and the RSB correction module, the DC offset correction module configured to correct a DC offset associated with the phase shifted I and Q current signals.

13. An apparatus comprising:
means for generating phase shifted in-phase (I) and quadrature-phase (Q) current signals; and
means for correcting residual sideband (RSB) error associated with the phase shifted I and Q current signals, the means for generating and the means for correcting are stacked to use a same current flow from a single connection to a power supply.

14. The apparatus of claim 13 , further comprising means for converting I and Q voltage signals to I and Q current signals that are input to the means for generating, the means for converting further stacked to use the same current flow from the single connection to the power supply.

15. The apparatus of claim 13 , the means for generating and the means for correcting form an array element, the apparatus comprising:
a plurality of the array elements forming a phased array transmitter, the plurality of array elements configured to transmit I and Q signals.

16. The apparatus of claim 13 , the means for generating and the means for correcting form an array element, the apparatus comprising:
a plurality of array elements forming a phased array receiver, the plurality of array elements configured to receive I and Q signals.

Assignees

• Lin Saihua
• Brockenbrough Roger
• Qualcomm Inc

Inventors

• Lin Saihua
• Brockenbrough Roger

Classifications

• H03D7/165 Primary

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title