Terminal circuit in inverter

Patent metadata

Field	Value
Publication number	US-9407167-B2
Application number	US-201514597068-A
Country	US
Kind code	B2
Filing date	Jan 14, 2015
Priority date	Jan 20, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A terminal circuit in an inverter is disclosed, the terminal circuit including a photo-coupler configured to electrically insulate input/output signals, to receive, as input, an open collector output signal or a pulse output signal from a first port and to output the open collector output signal or the pulse output signal to a second port through a first output terminal, a transistor in which a base (B) terminal is connected to a second output terminal of the photo-coupler. And a bias resistor connected to a base (B) terminal of the transistor and to an emitter (E) terminal.

First claim

What is claimed is:

1. A terminal circuit in an inverter, the terminal circuit comprising:
a photo-coupler configured to electrically insulate input/output signals, receive an open collector output signal or a pulse output signal from a first port and to output the received open collector output signal or pulse output signal to a second port via a first output terminal;
a pull-up resistor variably connected between the first output terminal and the second port, a resistance value of the pull-up resistor determined by a time constant;
a transistor having a base (B) terminal connected to a second output terminal of the photo-coupler; and
a bias resistor connected to the B terminal of the transistor and to an emitter (E) terminal of the transistor, a resistance value of the bias resistor determined such that a duty ratio of the pulse output signal is within a predetermined range,
wherein connection of the pull-up resistor is determined by a device using the pulse output signal as an input such that the pull-up resistor is not connected when the device receives an open collector-type pulse input and the pull-up resistor is connected when the device does not receive the open collector-type pulse input.

2. The terminal circuit of claim 1 , wherein the open collector output signal or pulse output signal is received from the first port by an inverter parameter input from a user input unit.

Assignees

• Lsis Co Ltd

Inventors

• Son Jubeom

Classifications

• H04B10/802

  for isolation, e.g. using optocouplers · CPC title

• B66C1/12 Primary

  Slings comprising chains, wires, ropes, or bands; Nets (article side grippers suspended by ropes or chains from crane hooks B66C1/42) · CPC title

• H03K17/795 Primary

  controlling bipolar transistors · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title