Method of manufacturing a photovoltaic device

US9406829B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9406829-B2
Application numberUS-201414317479-A
CountryUS
Kind codeB2
Filing dateJun 27, 2014
Priority dateJun 28, 2013
Publication dateAug 2, 2016
Grant dateAug 2, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a photovoltaic device comprising the steps of: providing a multilayer construct, the multilayer construct comprising a substrate having a thin-conductive oxide layer deposited thereon, a semiconductor absorber layer, and at least one semiconductor contact buffer layer; and annealing the semiconductor absorber layer or the semiconductor contact buffer layer with a laser or a flash lamp to form an alloy. 2. The method of claim 1 , wherein the annealing forms an alloy in the semiconductor absorber layer. 3. The method of claim 1 , wherein the annealing forms an alloy between the semiconductor absorber layer and the semiconductor contact buffer layer. 4. The method of claim 1 , wherein the annealing is performed with a UV flash lamp or a pulse UV laser. 5. The method of claim 1 , wherein the annealing is performed in an inert gas environment. 6. The method of claim 1 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor front contact buffer layer disposed between the substrate and the semiconductor absorber layer. 7. The method of claim 1 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer and the semiconductor absorber layer is disposed between the substrate and the semiconductor back contact buffer layer. 8. The method of claim 1 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor front contact buffer layer and a semiconductor back contact buffer layer, the semiconductor front contact buffer layer disposed between the substrate and the semiconductor absorber layer, and the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer. 9. The method of claim 8 , wherein the semiconductor absorber layer comprises CdTe, the semiconductor front contact buffer layer comprises CdS, and the semiconductor back contact buffer layer comprises CdS. 10. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises CdS and the annealing forms an alloy layer of CdS x Te 1-x between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 11. The method of claim 10 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor front contact buffer layer disposed between the substrate and the semiconductor absorber layer, and the annealing forms the alloy layer of CdS x Te 1-x in place of substantially all of the semiconductor front contact buffer layer. 12. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises ZnTe and the annealing forms an alloy layer of Cd 1-x Zn x Te between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 13. The method of claim 12 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer, the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer, and the annealing forms the alloy layer of Cd 1-x Zn x Te in place of substantially all of the semiconductor back contact buffer layer. 14. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises MnTe and the annealing forms an alloy layer of Cd 1-x Mn x Te between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 15. The method of claim 14 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer, the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer, and the annealing forms the alloy layer of Cd 1-x Mn x Te in place of substantially all of the semiconductor back contact buffer layer. 16. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises CdSe and the annealing forms an alloy layer of CdSe x Te 1-x between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 17. The method of claim 16 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer, the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer, and the annealing forms the alloy layer of CdSe x Te 1-x in place of substantially all of the semiconductor back contact buffer layer. 18. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises MgTe and the annealing forms an alloy layer of Cd 1-x Mg x Te between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 19. The method of claim 18 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer, the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer, and the annealing forms the alloy layer of Cd 1-x Mg x Te in place of substantially all of the semiconductor back contact buffer layer. 20. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and the at least one semiconductor contact buffer layer comprises HgTe and the annealing forms an alloy layer of Cd 1-x Hg x Te between the semiconductor absorber layer and the at least one semiconductor contact buffer layer. 21. The method of claim 20 , wherein the at least one semiconductor contact buffer layer comprises a semiconductor back contact buffer layer, the semiconductor absorber layer disposed between the substrate and the semiconductor back contact buffer layer, and the annealing forms the alloy layer of Cd 1-x Hg x Te in place of substantially all of the semiconductor back contact buffer layer. 22. The method of claim 1 , wherein the semiconductor absorber layer comprises CdTe and CdS. 23. The method of claim 1 , wherein the thin-conductive oxide layer comprises SnO2:F. 24. The method of claim 1 , wherein the annealing includes introducing the laser or the flash lamp to the semiconductor absorber layer or the semiconductor contact buffer layer from a side opposite the substrate. 25. The method of claim 1 , wherein the annealing includes controlling a depth of penetration of the energy of the laser or the flash lamp so that the energy does not contact other layers of the photovoltaic device. 26. A method of manufacturing a photovoltaic device comprising the steps of: providing a multilayer construct, the multilayer construct comprising a substrate having a thin-conductive oxide layer deposited thereon, a semiconductor absorber layer including CdTe, and a semiconductor front contact buffer layer including ZnTe, MnTe, MgTe, HgTe, or CdSe, the semiconductor front contact buffer layer disposed between the substrate and the semiconductor absorber layer; and annealing the semiconductor absorber layer or the semiconductor contact buffer layer with a laser or a flash lamp to form an alloy including Cd 1-x Zn x Te, Cd 1-x Mn x Te, Cd 1-x Mg x Te, Cd 1-x Hg x Te, or CdSe x Te 1-x .

Assignees

Inventors

Classifications

  • Annealing · CPC title

  • The active layers comprising only Group II-VI materials, e.g. CdS, ZnS or CdTe · CPC title

  • H10F10/162Primary

    comprising only Group II-VI materials, e.g. CdS/CdTe photovoltaic cells · CPC title

  • Electricity · mapped topic

  • H01L31/073Primary

    Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9406829B2 cover?
A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.
Who is the assignee on this patent?
First Solar Inc
What technology area does this patent fall under?
Primary CPC classification H10F10/162. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).