High temperature gate replacement process

Patent metadata

Field	Value
Publication number	US-9406776-B2
Application number	US-201414189342-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Dec 21, 2009
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.

First claim

What is claimed is:

1. A method comprising:
forming a gate structure that includes a dummy gate over a substrate;
forming a first interlayer dielectric layer over the dummy gate;
removing the dummy gate from the gate structure thereby forming a trench;
forming a gate electrode in the trench;
performing a first annealing process to adjust a threshold voltage of the gate electrode;
after performing the first annealing process, forming a second interlayer dielectric layer over the gate electrode such that the second interlayer dielectric layer physically contacts the gate electrode;
after performing the first annealing process to adjust the threshold voltage of the gate electrode, removing portions of the first and second interlayer dielectric layers to form a contact opening that extends through the first and second interlayer dielectric layers to expose a portion of the substrate; and
forming a silicide feature on the exposed portion of the substrate, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature.

2. The method of claim 1 , further comprising forming a heavily doped source/drain region adjacent the gate structure.

3. The method of claim 2 , wherein the first interlayer dielectric layer completely covers the heavily doped source/drain region while forming the gate electrode in the trench.

4. The method of claim 1 , forming a high-k dielectric material in the trench prior to forming the gate electrode in the trench.

5. A method comprising:
forming a gate structure over a substrate, wherein the gate structure includes a first gate electrode disposed over a first dielectric layer;
forming a first interlayer dielectric layer over the gate structure;
removing the first gate electrode from the gate structure thereby forming a trench;
forming a second gate electrode in the trench;
performing a first annealing process to adjust a threshold voltage of the second gate electrode;
after performing the first annealing process to adjust the threshold voltage of the second gate electrode, removing portions of the first interlayer dielectric layer to form a contact opening that extends through the first interlayer dielectric layer to expose a portion of the substrate; and
forming a silicide feature on the exposed portion of the substrate, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature.

6. The method of claim 5 , wherein removing the first gate electrode from the gate structure thereby forming the trench includes removing the first dielectric layer from the gate structure.

7. The method of claim 5 , further comprising forming a second dielectric material layer in the trench prior to forming the second gate electrode in the trench.

8. The method of claim 5 , wherein the first annealing process is performed at a first temperature and the second annealing process is performed at a second temperature that is different than the first temperature.

9. The method of claim 5 , further comprising forming a second interlayer dielectric layer over the second gate electrode after performing the first annealing process.

10. The method of claim 5 , further comprising forming a heavily doped source/drain region adjacent the gate structure, wherein the first interlayer dielectric layer completely covers the heavily doped source/drain region while forming the second gate electrode in the trench.

11. The method of claim 5 , further comprising forming a contact feature in the contact opening over the silicide feature.

12. A method comprising:
forming a gate structure that includes a dummy gate over a substrate;
forming a heavily doped source/drain feature in the substrate adjacent the dummy gate;
forming a first interlayer dielectric layer over the dummy gate such that the first interlayer dielectric layer completely covers the heavily doped source/drain feature;
removing the dummy gate from the gate structure thereby forming a trench;
forming a gate electrode in the trench while the first interlayer dielectric layer completely covers the heavily doped source/drain feature;
performing a first annealing process to adjust a threshold voltage of the gate electrode;
after performing the first annealing process, forming a second interlayer dielectric layer over the gate electrode such that the second interlayer dielectric layer physically contacts the gate electrode;
after performing the first annealing process to adjust the threshold voltage of the gate electrode, removing portions of the first and second interlayer dielectric layers to form a contact opening that extends through the first and second interlayer dielectric layers to expose a portion of the substrate; and
forming a silicide feature on the exposed portion of the substrate, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature.

13. The method of claim 12 , wherein the gate electrode has a top surface facing away from the substrate that is substantially coplanar with a top surface of the first interlayer dielectric layer that faces away from the top surface of the substrate.

14. The method of claim 12 , further comprising forming a lightly doped source/drain feature in the substrate adjacent the dummy gate.

15. The method of claim 14 , further comprising forming a contact etch stop layer over the dummy gate.

16. The method of claim 15 , wherein after forming the silicide feature, the contact etch stop layer physically contacts the lightly doped source/drain feature.

17. The method of claim 16 , wherein after forming the silicide feature, the contact etch stop layer physically contacts the heavily doped source/drain feature.

18. The method of claim 12 , further comprising forming a gate dielectric in the trench.

19. The method of claim 18 , wherein the gate dielectric and the gate electrode completely fill the trench.

20. The method of claim 12 , wherein the first interlayer dielectric layer completely covers the heavily doped source/drain feature until portions of the first and second interlayer dielectric layers are removed to form the contact opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Chung-Shi
• Yu Chen-Hua

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title