Semiconductor device having a breakdown voltage holding region

Patent metadata

Field	Value
Publication number	US-9406744-B2
Application number	US-201514919699-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Feb 2, 2011
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region.

First claim

The invention claimed is:

1. A semiconductor device including:
a semiconductor layer comprising a wide band gap semiconductor, and
a gate part which is formed at the semiconductor layer and sections the semiconductor layer into a plurality of cells,
wherein the cells include:
a first MIS transistor structure, which has a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region arranged in an order from a surface side of the semiconductor layer toward a reverse face side and has a first source trench formed so as to lie from the surface of the semiconductor layer through the source region and the channel region to the drain region with a deepest part thereof;
a p-n diode cell, which has a first breakdown voltage holding region of a second conductivity type formed selectively on an inner face of the first source trench and includes a p-n diode constructed by p-n junction between the first breakdown voltage holding region and the drain region; and
a Schottky cell in which a first conductivity-type Schottky region united with the drain region is exposed selectively, and
the semiconductor device further includes a source electrode, which is formed across the p-n diode cell and the Schottky cell, for forming an ohmic contact with the source region and forming a Schottky barrier lower than a diffusion potential of the body diode formed by p-n junction between the channel region and the drain region, with respect to the Schottky region.

2. The semiconductor device according to claim 1 , wherein the source electrode has a barrier formation layer, which is made of one compound selected from the group consisting of Ni, Ti, Al, Mo and polysilicon, at a contact part to contact the Schottky region.

3. The semiconductor device according to claim 1 , wherein
the first breakdown voltage holding region in the p-n diode cell is formed so as to lie from a bottom face of the first source trench along a side face of the source trench to the channel region, and
the p-n diode cell further includes a second conductivity-type channel contact region, which is formed on the bottom face of the first source trench and has an impurity concentration higher than an impurity concentration of the first breakdown voltage holding region.

4. The semiconductor device according to claim 1 , wherein
the first source trench in the p-n diode cell has a two-step structure including a first upper trench having a depth from the surface of the semiconductor layer to the channel region and a first lower trench having a width smaller than a width of the first upper trench and a depth from the channel region to the drain region, and
the p-n diode cell further includes a second conductivity-type channel contact region, which is formed at the channel region exposed to a step part between the first upper trench and the first lower trench and has an impurity concentration higher than an impurity concentration of the channel region.

5. The semiconductor device according to claim 1 , wherein
the Schottky cell has a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region arranged in an order from a surface side of the semiconductor layer toward a reverse face side and further includes a second MIS transistor structure having a second source trench formed to lie from the surface of the semiconductor layer through the source region and the channel region to the drain region and a second breakdown voltage holding region formed selectively at an edge part of the second source trench formed by intersection of a side face and a bottom face of the second source trench, and
the Schottky region is formed on a bottom face of the second source trench surrounded by the second breakdown voltage holding region.

6. The semiconductor device according to claim 5 , wherein the Schottky region is formed to have an area not to link with a depletion layer generated from a junction part of the Schottky region and the second breakdown voltage holding region.

7. The semiconductor device according to claim 1 , wherein the Schottky cell has an area larger than an area of the p-n diode cell.

8. The semiconductor device according to claim 5 , wherein
the second source trench in the Schottky cell has a two-step structure including a second upper trench having a depth from the surface of the semiconductor layer to the channel region and a second lower trench having a width smaller than a width of the second upper trench and a depth from the channel region to the drain region,
the second breakdown voltage holding region is formed so as to reach the channel region along a side face of the second lower trench, and
the Schottky cell further includes a second conductivity-type channel contact region, which is formed at the channel region exposed to a step part between the second upper trench and the second lower trench and has an impurity concentration higher than an impurity concentration of the channel region.

9. The semiconductor device according to claim 1 , wherein the gate part includes a gate trench formed at the semiconductor layer, a gate insulating film formed on an inner face of the gate trench, and a gate electrode formed at an inner side of the gate insulating film at the gate trench.

10. The semiconductor device according to claim 5 , wherein
the gate trench is formed in a lattice shape, and
the semiconductor device further includes a second conductivity-type relay region, which is formed across the p-n diode cell and the Schottky cell with an intersection part of the gate trench interposed therebetween, for connecting electrically the first breakdown voltage holding region with the second breakdown voltage holding region.

11. The semiconductor device according to claim 1 , wherein the gate part includes a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film.

12. The semiconductor device according to claim 1 , wherein the Schottky cell is surrounded by the p-n diode cells.

13. The semiconductor device according to claim 1 , wherein
the gate part is formed in a lattice shape so as to arrange p-n diode cells having the same size are arranged in a matrix manner, and
the Schottky cell has an area corresponding to an area of four or nine p-n diode cells.

14. The semiconductor device according to claim 1 , wherein the Schottky cell and the p-n diode cell include a quadrangular cell formed in a quadrangle.

15. The semiconductor device according to claim 1 , wherein the Schottky cell and the p-n diode cell include a hexagonal cell formed in a hexagon.

16. The semiconductor device according to claim 1 , wherein the Schottky cell and the p-n diode cell include a stripe cell formed in a stripe shape.

Assignees

• Rohm Co Ltd

Inventors

• Nakano Yuki

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/665

  having edge termination structures · CPC title

• H10D84/146

  the built-in components being Schottky barrier diodes · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title