Semiconductor device with counter doped layer

Patent metadata

Field	Value
Publication number	US-9406743-B2
Application number	US-201514706329-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	Mar 21, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n − -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n − -type drift layer with a silicon oxide film formed on the n − -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n − -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n − -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

First claim

What is claimed is:

1. A semiconductor device having a junction field effect transistor formed on a main surface of a semiconductor substrate of a first conductivity type, the device comprising:
a drift layer of the first conductivity type formed on the semiconductor substrate;
a plurality of source layers of the first conductivity type formed at predetermined intervals on a surface of the drift layer;
a plurality of trenches formed in the drift layer at regions between adjace…

Assignees

• Renesas Electronics Corp

Inventors

• Kagotoshi Yasuaki
• Arai Koichi
• Yokoyama Natsuki
• Shimizu Haruka

Classifications

• H10D30/051

  Electricity · mapped topic

• H10D30/831 Primary

  Electricity · mapped topic

• H10D64/411

  Electricity · mapped topic

• H10D62/8325

  Electricity · mapped topic

• H10D62/343

  Electricity · mapped topic