Silicon process compatible trench magnetic device

Patent metadata

Field	Value
Publication number	US-9406740-B2
Application number	US-201514745703-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Mar 7, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench.

First claim

What is claimed is:

1. An integrated inductor in a semiconductor, the integrated inductor comprising:
a closed loop trench in a substrate, wherein the trench is formed with sidewalls connected by a bottom surface in the substrate;
a first insulator layer deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface;
a conductor layer deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench;
a second insulator layer deposited on top of the conductor layer on the sidewalls and the bottom surface of the trench; and
a first magnetic layer deposited on the sidewalls and the bottom surface of the trench so as to coat the second insulator layer in the trench without filling the trench;
wherein the first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench;
wherein an interior conductor path is formed by the conductor layer at an inside wall of the trench, such that the interior conductor path connects to a first exterior conductor connection;
wherein a second exterior conductor connection separately connects to the conductor layer formed on an outside wall of the trench; and
wherein an electrical path from the first exterior conductor connection to the second exterior conductor connection by way of the conductor layer in the trench forms a continuous electrical path that passes through the inner and outer closed magnetic loops.

2. The integrated inductor of claim 1 , wherein the first exterior conductor connection and the second exterior conductor connection are an elongated pattern wiring trace of the conductor layer applied on a top surface of the substrate; and
wherein the closed loop trench is a circular trench.

3. The integrated inductor of claim 2 , wherein the elongated pattern wiring trace of the conductor layer is concurrently deposited on the top surface of substrate that is not in the trench when depositing the conductor layer inside the trench.

4. The integrated inductor of claim 1 , further comprising a third insulator layer deposited on the sidewalls and the bottom surface of the trench so as to coat the first magnetic layer in the trench without filling the trench; and
a second magnetic layer deposited on the sidewalls and the bottom surface of the trench so as to coat the third insulator layer in the trench without filling the trench.

5. The integrated inductor of claim 1 , further comprising applying a magnetic field aligned perpendicular to a plane of the substrate while depositing the first magnetic layer thereby causing the first magnetic layer to have an anisotropy;
wherein the anisotropy is perpendicular to the plane of the substrate.

Assignees

• IBM

Inventors

• Wang Naigang
• Webb Bucknell C

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title