Image sensor pixel cell with non-destructive readout

Patent metadata

Field	Value
Publication number	US-9406718-B2
Application number	US-201414500193-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Sep 29, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.

First claim

What is claimed is:

1. A pixel cell, comprising:
a photodiode coupled to photogenerate image charge in response to incident light;
a deep trench isolation structure disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure, wherein the deep trench isolation structure includes a conductive material, and an oxide material lining an interior of the deep trench isolation structure;
an amplifier transistor coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure;
a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor;
a floating diffusion coupled to the amplifier transistor;
a transfer transistor coupled between the photodiode and the floating diffusion to selectively couple the floating diffusion to the photodiode;
a reset transistor coupled to the floating diffusion to selectively reset charge in the floating diffusion and the photodiode; and
a switch transistor coupled between the deep trench isolation structure and the floating diffusion, wherein the amplifier transistor and the reset transistor are selectively coupled to the deep trench isolation structure through the switch transistor.

2. The pixel cell of claim 1 wherein the amplifier transistor is a first amplifier transistor, wherein the row select transistor is a first row select transistor, and wherein the amplified image data selectively output by the first row select transistor is first amplified image data, the pixel cell further comprising: a second amplifier transistor coupled to the floating diffusion to generate second amplified image data in response to the image charge read out from the photodiode through the floating diffusion; and a second row select transistor coupled to an output of the second amplifier transistor to selectively output the second amplified image data to the column bitline coupled to the second row select transistor.

3. The pixel cell of claim 2 wherein the reset transistor is further coupled to the deep trench isolation structure to selectively reset charge in the deep trench isolation structure.

4. The pixel cell of claim 1 wherein the conductive material comprises polysilicon.

5. The pixel cell of claim 4 wherein the oxide material is a charged oxide trench liner.

6. An imaging system, comprising:
a pixel array including a plurality of pixel cells, wherein each one of the pixel cells includes:
a photodiode coupled to photogenerate image charge in response to incident light;
a deep trench isolation structure disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure, wherein the deep trench isolation structure includes a conductive material, and an oxide material lining an interior of the deep trench isolation structure;
an amplifier transistor coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure;
a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor;
a floating diffusion coupled to the amplifier transistor;
a transfer transistor coupled between the photodiode and the floating diffusion to selectively couple the floating diffusion to the photodiode;
a reset transistor coupled to the floating diffusion to selectively reset charge in the floating diffusion and the photodiode; and
a switch transistor coupled between the deep trench isolation structure and the floating diffusion, wherein the amplifier transistor and the reset transistor are selectively coupled to the deep trench isolation structure through the switch transistor;

control circuitry coupled to the pixel array to control operation of the pixel array; and
readout circuitry coupled to the pixel array to read out the amplified image data from each one of the plurality of pixel cells of the pixel array.

7. The imaging system of claim 6 further comprising function logic coupled to the readout circuitry to store the amplified image data read out from the pixel array.

8. The imaging system of claim 6 wherein the amplifier transistor is a first amplifier transistor, wherein the row select transistor is a first row select transistor, and wherein the amplified image data selectively output by the first row select transistor is first amplified image data, wherein each one of the pixel cells further comprises: a second amplifier transistor coupled to the floating diffusion to generate second amplified image data in response to the image charge read out from the photodiode through the floating diffusion; and a second row select transistor coupled to an output of the second amplifier transistor to selectively output the second amplified image data to the column bitline coupled to the second row select transistor.

9. The imaging system of claim 8 wherein the reset transistor is further coupled to the deep trench isolation structure to selectively reset charge in the deep trench isolation structure.

10. The imaging system of claim 6 wherein the conductive material comprises polysilicon.

11. The imaging system of claim 10 wherein the oxide material is a charged oxide trench liner.

Assignees

• Omnivision Tech Inc

Inventors

• Solhusvik Johannes
• Massetti Dominic

Classifications

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N23/71

  Circuitry for evaluating the brightness variation · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/532

  by controlling global shutters in CMOS SSIS · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title