Methods for fabricating and using nanowires

Patent metadata

Field	Value
Publication number	US-9406709-B2
Application number	US-96651410-A
Country	US
Kind code	B2
Filing date	Dec 13, 2010
Priority date	Jun 22, 2010
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Methods, apparatuses, systems, and devices relating to fabricating one or more nanowires are disclosed. One method for fabricating a nanowire includes: selecting a particular wavelength of electromagnetic radiation for absorption for a nanowire; determining a diameter corresponding to the particular wavelength; and fabricating a nanowire having the determined diameter. According to another embodiment, one or more nanowires may be fabricated in an array, each having the same or different determined diameters. An image sensor and method of imaging using such an array are also disclosed.

First claim

What is claimed is:

1. A method for fabricating a nanowire comprising:
selecting a particular wavelength of electromagnetic radiation for absorption for a nanowire;
determining a diameter corresponding to the particular wavelength, wherein the nanowire with the determined diameter has an absorption peak of electromagnetic radiation at the particular wavelength; and
fabricating the nanowire having the determined diameter.

2. The method according to claim 1 , the particular wavelength is within one of the ultraviolet (UV), visible (VIS) or infrared (IR) spectra.

3. The method according to claim 1 , wherein the diameter of the nanowire is between about 90 and 150 nm, and the particular wavelength is in the visible spectrum.

4. The method according to claim 1 , wherein the length of the nanowire is between about 1 and 10 μm.

5. The method according to claim 1 , wherein there is a nearly linear relationship between nanowire diameter and the wavelength of electromagnetic radiation for absorption of the nanowire.

6. The method according to claim 1 , wherein the nanowire is fabricated by a dry etching process or a vapor-liquid-solid (VLS) method.

7. The method according to claim 1 , wherein the nanowire is fabricated from a silicon or indium arsenide wafer.

8. The method according to claim 1 , wherein fabricating the nanowire comprises using a mask having the diameter.

9. The method according to claim 1 , further comprising:
fabricating an array of nanowires, wherein at least one of the nanowires in the array has the same or a different determined diameter than another of the nanowires in the array.

10. The method according to claim 1 , wherein the cross-sectional shape of the nanowire is substantially circular.

11. The method according to claim 1 , the nanowire is fabricated upon the substrate and the substrate is a silicon-on-insulator or silicon-on-glass substrate.

12. The method according to claim 1 , further comprising depositing a cladding material around the nanowire.

13. The method according to claim 1 , further comprising fabricating an array of nanowires.

14. The method according to claim 11 , wherein, (i) the substrate has an intrinsic epitaxial (epi) layer and a thin n+ layer at an oxide interface; (ii) the substrate has a lightly doped n epi layer and a thin n+ layer at an oxide interface. (iii) the substrate has a lightly doped p epi layer and a thin p+ layer at an oxide interface, or (iv) the substrate has an intrinsic epi layer and a thin p+ layer at and oxide interface.

15. The method according to claim 11 , wherein p+ or n+ ion implantation is employed to form a shallow junction at a top layer of the substrate to formed one of a p-i-n, p-n, n-i-p, n-p diode.

16. The method according to claim 11 , wherein one or more transistors are formed on the substrate for controlling the photocharge transfer from the nanowire to a readout circuit (ROC) or other electronics.

17. The method of claim 1 , wherein the nanowire is essentially vertical to a substrate.

18. The method according to claim 13 , wherein size of the array is about 100 μm×100 μm or larger.

19. The method according to claim 13 , wherein the nanowires are spaced apart at a pitch of about 1 μm or less in the x- and y-directions.

20. The method of claim 13 , wherein the nanowire is essentially vertical to a substrate.

Assignees

• Seo Kwanyong
• Steinvurzel Paul
• Schonbrun Ethan
• Wober Munib
• Crozier Kenneth B
• Harvard College
• Zena Tech Inc

Inventors

• Seo Kwanyong
• Steinvurzel Paul
• Schonbrun Ethan
• Wober Munib
• Crozier Kenneth B

Classifications

• G02B6/107 Primary

  Subwavelength-diameter waveguides, e.g. nanowires · CPC title

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H10F39/8067

  Reflectors · CPC title

• B82Y20/00 Primary

  Nanooptics, e.g. quantum optics or photonic crystals · CPC title

• H01L27/14629 Primary

  Electricity · mapped topic