Semiconductor device, and display device and electronic device having the same

Patent metadata

Field	Value
Publication number	US-9406699-B2
Application number	US-201314143535-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Jan 7, 2006
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a first element;
a first switch;
a first wiring; and
a second wiring,
wherein one of a source and a drain of the first transistor is configured to be supplied with a first potential,
wherein the other of the source and the drain of the first transistor is configured to be supplied with a first signal,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring configured to be supplied with a second signal,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein a first terminal of the first element is electrically connected to the second wiring configured to be supplied with a third signal,
wherein a second terminal of the first element is electrically connected to a gate of the second transistor,
wherein a first terminal of the first switch is configured to be supplied with the first potential, and
wherein a second terminal of the first switch is electrically connected to the gate of the second transistor.

2. The semiconductor device according to claim 1 , further comprising a third transistor,
wherein one of a source and a drain of the third transistor is configured to be supplied a fourth potential, and
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor.

3. The semiconductor device according to claim 2 , further comprising a fifth transistor,
wherein one of a source and a drain of the fifth transistor is configured to be supplied with the first potential,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, and
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

4. The semiconductor device according to claim 1 , further comprising:
a third transistor; and
a fourth transistor,
wherein one of a source and a drain of the third transistor is configured to be supplied with a second potential,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein one of a source and a drain of the fourth transistor is configured to be supplied with the second potential,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor, and
wherein a gate of the fourth transistor is configured to be supplied with a fourth signal.

5. The semiconductor device according to claim 4 , further comprising a fifth transistor,
wherein one of a source and a drain of the fifth transistor is configured to be supplied with the first potential,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, and
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

6. The semiconductor device according to claim 1 , further comprising:
a third transistor; and
a fourth transistor,
wherein one of a source and a drain of the third transistor is configured to be supplied with a fourth signal,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein one of a source and a drain of the fourth transistor is configured to be supplied with a second potential,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the third transistor, and
wherein a gate of the fourth transistor is configured to be supplied with a fifth signal.

7. The semiconductor device according to claim 6 , further comprising a fifth transistor,
wherein one of a source and a drain of the fifth transistor is configured to be supplied with the first potential,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, and
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

8. The semiconductor device according to claim 1 ,
wherein the first element is configured to generate a voltage when a current flows in the first element,
wherein the first transistor is configured to be turned on when a third potential of the second signal is applied to the gate of the first transistor,
wherein the first transistor is configured to be turned off when a fourth potential of the second signal is applied to the gate of the first transistor.

9. The semiconductor device according to claim 1 , wherein the first element is a transistor.

10. A display device comprising:
the semiconductor device according to claim 1 ; and
a pixel,
wherein the pixel comprises a display element, and
wherein the pixel is electrically connected to other of the source and the drain of the first transistor.

11. A display device comprising:
the semiconductor device according to claim 1 ; and
a pixel,
wherein the pixel comprises a light-emitting element, and
wherein the pixel is electrically connected to other of the source and the drain of the first transistor.

12. A display device comprising:
the semiconductor device according to claim 1 ; and
a pixel,
wherein the pixel comprises a liquid crystal element, and
wherein the pixel is electrically connected to other of the source and the drain of the first transistor.

13. A display module comprising:
the semiconductor device according to claim 1 ; and
a flexible printed circuit.

14. An electronic appliance comprising:
the display module according to claim 13 ;
an operation switch; and
a battery or a speaker.

15. A semiconductor device comprising:
a first transistor;
a second transistor;
a first element;
a first switch;
a first wiring;
a second wiring;
a third wiring; and
a fourth wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,
wherein a first terminal of the first element is electrically connected to the fourth wiring,
wherein a second terminal of the first element is electrically connected to a gate of the second transistor,
wherein a first terminal of the first switch is electrically connected to the first wiring,
wherein a second terminal of the first switch is electrically connected to the gate of the second transistor,
wherein the first wiring is configured to be supplied with a first potential,
wherein the second wiring is configured to be supplied with a first signal,
wherein the third wiring is configured to be supplied with a second signal, and
wherein the fourth wiring is configured to be supplied with a third signal that is different from the second signal.

16. The semiconductor device according to claim 15 , further comprising:
a third transistor; and
a fifth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the fifth

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K19/00369

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title