Method and gate structure for threshold voltage modulation in transistors

Patent metadata

Field	Value
Publication number	US-9406678-B2
Application number	US-201414213420-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Nov 4, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
preparing a substrate including a PMOS region and an NMOS region;
forming a high-k dielectric layer over the substrate;
forming a threshold voltage modulation layer over the high-k dielectric layer of the NMOS region;
forming a first work function layer over the threshold voltage modulation layer of the NMOS region and the high-k dielectric layer of the PMOS region;
forming, in-situ, an oxidation suppressing layer over the first work function layer of the NMOS region without an air break after the forming of the first work function layer;
forming a second work function layer over the oxidation suppressing layer and the first work function layer of the PMOS region;
forming, over the PMOS region of the substrate, a first gate stack that includes the high-k dielectric layer, the first work function layer and the second work function layer; and
forming, over the NMOS region of the substrate, a second gate stack which includes the high-k dielectric layer, the threshold voltage modulation layer, the first work function layer, the oxidation suppressing layer and the second work function layer,
wherein the oxidation suppressing layer is formed only the second gate stack.

2. The method according to claim 1 , wherein the preparing the substrate comprises:
forming a germanium-containing channel region over the PMOS region of the substrate.

3. The method according to claim 2 , wherein the forming a germanium-containing channel region comprises:
epitaxially growing a silicon-germanium layer; and
epitaxially growing a silicon layer over the silicon-germanium layer.

4. The method according to claim 1 , wherein, after the forming of the second work function layer, the method further comprising:
forming a capping layer over the second work function layer; and
forming, over the capping layer, a low resistance layer to reduce a resistance of the first gate stack and the second gate stack.

5. The method according to claim 1 , wherein the forming the oxidation suppressing layer over the first work function layer of the NMOS region comprises:
forming, in-situ, a silicon layer over the first work function layer without exposing the silicon layer to ambient atmosphere;
forming, over the silicon layer, a mask layer that exposes the PMOS region; and
removing the silicon layer from the PMOS region via the mask layer.

6. The method according to claim 1 , wherein, in the forming of the second work function layer comprises:
oxidizing a surface of the first work function layer of the PMOS region.

7. The method according to claim 1 , wherein the first work function layer and the second work function layer comprise titanium nitrides with the same work function.

8. The method according to claim 1 , wherein the forming the threshold voltage modulation layer comprises:
forming a lanthanum-based oxide that contains a lanthanum series element.

9. A method for fabricating a semiconductor device, the method comprising:
preparing a substrate including a PMOS region and an NMOS region;
forming a germanium-containing channel region over the PMOS region of the substrate;
forming a high-k dielectric layer over the substrate;
forming, over the high-k dielectric layer of the NMOS region, a threshold voltage modulation layer that includes a lanthanum series element;
forming a first titanium nitride layer over the threshold voltage modulation layer of the NMOS region and the high-k dielectric layer of the PMOS region;
forming, over the first titanium nitride layer of the NMOS region, an oxidation suppressing layer that contains silicon without an air break after the forming of the first titanium nitride layer;
forming a second titanium nitride layer over the oxidation suppressing layer and the first titanium nitride layer of the PMOS region;
forming, over the PMOS region of the substrate, a first gate stack that includes the high-k dielectric layer, the first titanium nitride layer and the second titanium nitride layer, over the PMOS region of the substrate; and
forming, over the NMOS region of the substrate, a second gate stack that includes the high-k dielectric layer, the threshold voltage modulation layer, the first titanium nitride layer, the oxidation suppressing layer and the second titanium nitride layer,
wherein the oxidation suppressing layer is formed only the second gate stack.

10. The method according to claim 9 , wherein, after the forming of the second titanium nitride, the method further comprises:
forming a polysilicon capping layer over the second titanium nitride; and
forming a metal silicide layer over the polysilicon capping layer.

11. The method according to claim 9 , wherein the forming the threshold voltage modulation layer comprises:
forming a lanthanum oxide layer.

12. The method according to claim 9 , wherein the forming the oxidation suppressing layer over the first titanium nitride of the NMOS region comprises:
forming, in-situ, a silicon layer over the first titanium nitride without an exposure to ambient atmosphere;
forming, over the silicon layer, a mask layer that exposes the PMOS region; and
removing, via the mask layer, the silicon layer from the PMOS region.

13. The method according to claim 9 , wherein, in the forming of the second titanium nitride comprises:
oxidizing a surface of the first titanium nitride of the PMOS region.

14. The method according to claim 9 , wherein the first titanium nitride and the second titanium nitride are formed of titanium nitrides with the same work function.

15. The method according to claim 9 , wherein the forming a germanium-containing channel region comprises:
epitaxially growing a silicon-germanium layer; and
epitaxially growing a silicon layer over the silicon-germanium layer.

Assignees

• Sk Hynix Inc

Inventors

• Ji Yun-Hyuck
• Joo Moon-Sig
• Jang Se-Aug
• Lee Seung-Mi
• Kim Hyung-Chul

Classifications

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title