Stacked semiconductor die assemblies with die support members and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9406660-B2
Application number	US-201414264699-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Apr 29, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

First claim

We claim:

1. A semiconductor die assembly, comprising:
a package substrate including a plurality of bond pads arranged in a first array and a plurality of bond pads arranged in a second array that is adjacent and perpendicular to the first array of bond pads;
a first semiconductor die attached to the package substrate;
a support member attached to the package substrate, wherein the support member is separated from the first semiconductor die on the package substrate;
a second semiconductor die having one region coupled to the support member and another region coupled to the first semiconductor die, wherein a portion of the first semiconductor die extends beyond a perimeter of the second semiconductor die;
a first wirebond connector connecting a first bond pad of the first array of bond pads to the portion of the first semiconductor die;
a second wirebond connector connecting a second bond pad of the second array of bond pads to the portion of the first semiconductor die; and
a third wirebond connector connecting a third bond pad of the first array of bond pads to the second semiconductor die, wherein the third wirebond connector extends over the second wirebond connector, and wherein the third wirebond connector is transverse to the second wirebond connector.

2. The semiconductor die assembly of claim 1 wherein the support member, the first and second semiconductor dies, and the package substrate together define a cavity beneath the second semiconductor die, and wherein the semiconductor die assembly further comprises a package casing that includes an encapsulant at least partially extending into the cavity.

3. The semiconductor die assembly of claim 1 , further comprising a die-attach film attaching the first semiconductor die to the package substrate.

4. The semiconductor die assembly of claim 3 , further comprising another die-attach film attaching the support member to the package substrate.

5. The semiconductor die assembly of claim 1 , further comprising a die-attach film attaching both the support member and the first semiconductor die to the second semiconductor die.

6. The semiconductor die assembly of claim 1 , further comprising:
a first die-attach material attaching the first semiconductor die to the package substrate;
a second die-attach material attaching the support member to the package substrate; and
a third die-attach material attaching both the support member and the first semiconductor die to the second semiconductor die.

7. The semiconductor die assembly of claim 6 wherein the first, second, and third die-attach materials each include a die-attach film.

8. The semiconductor die assembly of claim 1 , further comprising a fourth wirebond connector connecting a fourth bond of the second array of bond pads to the second semiconductor die, wherein the third wirebond connector extends over the wirebond connector.

9. The semiconductor die assembly of claim 1 wherein the third bond pad is adjacent the first bond pad.

10. The semiconductor die assembly of claim 1 , further comprising a fourth wirebond connector connecting a fourth bond of the first array of bond pads to the second semiconductor die, wherein the first bond pad is between the third and fourth bond pads.

11. The semiconductor die assembly of claim 1 wherein: the first semiconductor die is a controller die; and
the second semiconductor die is a memory die.

12. A semiconductor die assembly, comprising:
a package substrate including a plurality of bond pads arranged in a first array along a first axis and a plurality of bond pads arranged in a second array along a second axis that is transverse to the first axis;
a first semiconductor die attached to the package substrate;
a support member attached to the package substrate, wherein the support member is separated from the first semiconductor die on the package substrate;
a second semiconductor die attached to the support member and the first semiconductor die, wherein the first and second semiconductor dies, the support member, and the package substrate together define a cavity beneath the second semiconductor die, and wherein a portion of the first semiconductor die is outside of the cavity;
a first wirebond connector connecting a first bond pad of the first array of bond pads to the portion of the first semiconductor die;
a second wirebond connector connecting a second bond pad of the second array of bond pads to the portion of the first semiconductor die; and
a third wirebond connector connecting a third bond pad of the first array of bond pads to the second semiconductor die, wherein the third wirebond connector extends over the second wirebond connector, and wherein the third wirebond connector is transverse to the second wirebond connector.

13. The semiconductor die assembly of claim 1 , further comprising a fourth wirebond connector connecting a fourth bond of the second array of bond pads to the second semiconductor die, wherein the third wirebond connector extends over the fourth wirebond connector.

14. The semiconductor die assembly of claim 1 , further comprising a package casing that includes an encapsulant at least partially extending into the cavity.

Assignees

• Micron Technology Inc

Inventors

• Ye Seng Kim
• Ng Hong Wan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title