Conductor strip with contact areas having cutouts

Patent metadata

Field	Value
Publication number	US-9406592-B2
Application number	US-201514735300-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 10, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts.

First claim

What is claimed is:

1. A power semiconductor circuit comprising:
at least one semiconductor having at least one contact area;
at least one bonding conductor strip comprising at least one contact region fastened on at least one of the contact areas; and
an array of cutouts in the at least one contact region of the at least one bonding conductor strip;
wherein the array of cutouts is distributed at a first uniform density in a center area of the at least one contact region and at a second uniform density outside of the center area; and
wherein the first uniform density is lower than the second uniform density.

2. The power semiconductor circuit of claim 1 , wherein:
the cutouts extend through the bonding conductor strip, or
the cutouts extend only over part of a thickness of the bonding conductor strip and form a depression.

3. The power semiconductor circuit of claim 1 , wherein the cutouts have:
(a) a circular or oval cross section,
(b) a polygonal cross section, or
(c) a form of a continuous groove having a longitudinal direction that extends along a straight line, along a curved line, along an arc of a circle, or along a line with straight sections that are angled with respect to one another.

4. The power semiconductor circuit of claim 1 , wherein the cutouts are distributed over an area section of the contact region that makes up at least 50% of the contact region.

5. The power semiconductor circuit of claim 1 , wherein the contact regions of the bonding conductor strip are connected to the contact areas via a sintered connecting layer.

6. The power semiconductor circuit of claim 1 , further comprising conductor tracks having at least one contact section, wherein at least one contact region of the bonding conductor strip is fastened on the at least one contact section via a sintered connecting layer.

7. The power semiconductor circuit of claim 1 , further comprising a printed circuit board on which the contact area of the semiconductor is fastened by a sintered layer,
wherein the contact region of the bonding conductor strip is fastened by a further sintered layer on a further one of the contact areas of the semiconductor, and
wherein, with respect to the semiconductor, the further contact area is opposite the contact area that is fastened on the printed circuit board.

8. The power semiconductor circuit of claim 1 , wherein the cutouts are distributed over an area section of the contact region that makes up at least 75% of the contact region.

9. The power semiconductor circuit of claim 1 , wherein the cutouts are distributed over an area section of the contact region that makes up at least 90% of the contact region.

10. A method for producing a power semiconductor circuit comprising:
producing an array of cutouts in a region of a bonding conductor strip;
wherein the array of cutouts is distributed at a first uniform density in a center area of the at least one contact region and at a second uniform density outside of the center area;
wherein the first uniform density is lower than the second uniform density; and
fastening the region of the bonding conductor strip in which the cutouts have been produced, as a contact region, on a contact area of a semiconductor or on a contact section of a conductor track.

11. The method of claim 10 , wherein the fastening comprises:
applying sintering compound as green body to the contact area or to the contact section,
pressing the contact region of the bonding conductor strip onto the sintering compound, and
subsequently sintering the sintering compound.

12. The method of claim 11 , further comprising:
applying a sintering compound to a conductor track section of a printed circuit board, and
pressing the semiconductor onto the sintering compound,
wherein the step of applying the sintering compound to the contact area of the semiconductor is then performed.

13. The method of claim 10 , wherein:
the cutouts extend through the bonding conductor strip, or
the cutouts extend only over part of a thickness of the bonding conductor strip and form a depression.

14. The method of claim 10 , wherein the cutouts have:
(a) a circular or oval cross section,
(b) a polygonal cross section, or
(c) a form of a continuous groove having a longitudinal direction that extends along a straight line, along a curved line, along an arc of a circle, or along a line with straight sections that are angled with respect to one another.

15. The method of claim 10 , wherein the cutouts are distributed over an area section of the contact region that makes up at least 50% of the contact region.

16. The method of claim 10 , wherein the contact regions of the bonding conductor strip are connected to the contact areas via a sintered connecting layer.

17. The method of claim 10 , wherein the power semiconductor circuit further comprises conductor tracks having at least one contact section, wherein at least one contact region of the bonding conductor strip is fastened on the at least one contact section via a sintered connecting layer.

18. The method of claim 10 , wherein the power semiconductor circuit further comprises a printed circuit board on which the contact area of the semiconductor is fastened by a sintered layer,
wherein the contact region of the bonding conductor strip is fastened by a further sintered layer on a further one of the contact areas of the semiconductor, and
wherein, with respect to the semiconductor, the further contact area is opposite the contact area that is fastened on the printed circuit board.

Assignees

• Continental Automotive Gmbh

Inventors

• Kohl Nico
• Metzler Martin
• Egelkraut Sven
• Leicht Markus

Classifications

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/761

  of strap connectors · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07653

  changes in shapes · CPC title