Semiconductor device and method of controlling warpage in semiconductor package

US9406579B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9406579-B2
Application numberUS-201213471314-A
CountryUS
Kind codeB2
Filing dateMay 14, 2012
Priority dateMay 14, 2012
Publication dateAug 2, 2016
Grant dateAug 2, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.

First claim

Opening claim text (preview).

What is claimed: 1. A method of making a semiconductor device, comprising: forming an insulating layer over a surface of a substrate; forming a conductive layer completely above the surface of the substrate in the insulating layer; disposing a semiconductor die over the substrate with an active surface of the semiconductor die oriented toward the substrate; forming a channel in the insulating layer extending to the surface of the substrate around the semiconductor die; depositing an underfill material between the semiconductor die and the substrate and in the channel wherein a portion of the insulating layer between a footprint of the semiconductor die and the channel is devoid of the underfill material; and disposing a heat spreader over the semiconductor die with the heat spreader thermally connected to the substrate. 2. The method of claim 1 , further including forming a thermal interface material over the semiconductor die. 3. The method of claim 1 , further including depositing the underfill material between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. 4. The method of claim 1 , further including depositing the underfill material between the semiconductor die and the substrate along a first, second, third, and fourth edge of the semiconductor die. 5. A method of making a semiconductor device, comprising: forming an insulating layer over a surface of a substrate; forming a conductive layer over the surface of the substrate; disposing a semiconductor die over the substrate with an active surface of the semiconductor die oriented toward the substrate; forming a channel in the insulating layer extending to the surface of the substrate around the semiconductor die; and depositing an underfill material between the semiconductor die and the substrate and in the channel wherein a portion of the insulating layer between a footprint of the semiconductor die and the channel is devoid of the underfill material. 6. The method of claim 5 , further including forming a thermal interface material over the semiconductor die. 7. The method of claim 5 , further including disposing a heat spreader over the semiconductor die with the heat spreader thermally connected to the substrate. 8. The method of claim 5 , further including depositing the underfill material between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. 9. The method of claim 5 , further including depositing the underfill material between the semiconductor die and the substrate along a first, second, third, and fourth edge of the semiconductor die. 10. A semiconductor device, comprising: a substrate including first and second opposing surfaces; a conductive via formed through the substrate extending from the first surface of the substrate to the second surface of the substrate; an insulating layer formed over the first surface of the substrate; a conductive layer formed entirely above the first surface of the substrate in the insulating layer and over the conductive via; a semiconductor die disposed over the first surface of the substrate and contacting the conductive layer; a channel formed in the insulating layer outside a footprint of the semiconductor die extending to the first surface of the substrate surrounding the semiconductor die; an underfill material deposited between the semiconductor die and the substrate and in the channel wherein a portion of the insulating layer between the footprint of the semiconductor die and the channel is devoid of the underfill material; and a heat spreader disposed over the semiconductor die with the heat spreader thermally connected to the substrate. 11. The semiconductor device of claim 10 , further including a thermal interface material formed over the semiconductor die. 12. The semiconductor device of claim 10 , wherein the underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. 13. A semiconductor device, comprising: a substrate; an insulating layer formed over a surface of the substrate; a conductive layer formed completely over the surface of the substrate in the insulating layer; a semiconductor die disposed over the substrate including an active surface of the semiconductor die oriented toward the surface of the substrate; a channel formed in the insulating layer extending to the surface of the substrate around the semiconductor die; and an underfill material deposited between the semiconductor die and the substrate and in the channel wherein a portion of the insulating layer between a footprint of the semiconductor die and the channel is devoid of the underfill material. 14. The semiconductor device of claim 13 , wherein a thermal interface material is formed over the semiconductor die. 15. The semiconductor device of claim 13 , wherein the underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. 16. The semiconductor device of claim 13 , wherein the underfill material is deposited between the semiconductor die and the substrate along a first, second, third, and fourth edge of the semiconductor die. 17. A semiconductor device, comprising: a substrate; a semiconductor die disposed over the substrate; an insulating layer formed over a surface of the substrate; a channel formed in the insulating layer outside of a footprint of the semiconductor die extending to the surface of the substrate around the semiconductor die; and an underfill material deposited between the semiconductor die and the substrate and in the channel wherein a portion of the insulating layer between the footprint of the semiconductor die and the channel is devoid of the underfill material. 18. The semiconductor device of claim 17 , wherein a thermal interface material is formed over the semiconductor die. 19. The semiconductor device of claim 17 , wherein the underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. 20. The semiconductor device of claim 17 , wherein the underfill material is deposited between the semiconductor die and the substrate along a first, second, third, and fourth edge of the semiconductor die. 21. The method of claim 1 , further including disposing a discrete electrical device within the channel. 22. The method of claim 5 , further including disposing a discrete electrical device within the channel. 23. The semiconductor device of claim 10 , further including a discrete electrical device disposed within the channel. 24. The semiconductor device of claim 13 , further including a discrete electrical device disposed within the channel. 25. The semiconductor device of claim 17 , further including a discrete electrical device disposed within the channel. 26. The semiconductor device of claim 17 , further including a heat spreader disposed over the semiconductor die with the heat spreader thermally connected to the substrate.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • relative to the surface, e.g. recessed, protruding · CPC title

  • Die-attach connectors and bond wires · CPC title

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Frequently asked questions

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What does patent US9406579B2 cover?
A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor d…
Who is the assignee on this patent?
Choi Daesik, Yang Joungin, Park Sang Mi, and 3 more
What technology area does this patent fall under?
Primary CPC classification H10W74/114. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).