FinFET device

Patent metadata

Field	Value
Publication number	US-9406570-B2
Application number	US-201514696534-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Jan 5, 2012
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.

First claim

What is claimed is:

1. A field effect transistor device comprising:
a substrate;
a first insulator layer disposed on the substrate;
a semiconductor layer disposed on the first insulator layer;
a second insulator layer disposed on the semiconductor layer;
a first finFET device, having a first fin and a first dielectric layer, the first fin disposed on and in contact with the first insulator layer and the first dielectric layer surrounds the first fin and is disposed on an in contact with the first insulator layer;
a second finFET device, having a second fin and a second dielectric layer, the second fin disposed on and in contact with the second insulator layer and the second dielectric layer surrounds the second fin and is disposed on and in contact with the second insulator layer; and
a hardmask layer disposed between a top surface of the first fin and the first dielectric layer, and another hardmask layer disposed between the second fin and the second dielectric layer.

2. The device of claim 1 , wherein the first finFET device includes the first fin formed from a first semiconductor material of the semiconductor layer and the first dielectric layer arranged substantially perpendicular to the first fin, and the second finFET device includes the second fin formed from a second semiconductor material and the dielectric layer arranged substantially perpendicular to the second fin, wherein the first fin of the first finFET device is substantially parallel to the second fin of the second finFET device.

3. The device of claim 2 , wherein the first semiconductor material is arranged with a first crystalline orientation, and the second semiconductor material is arranged with a second crystalline orientation, the first crystalline orientation is dissimilar from the second crystalline orientation.

4. The device of claim 2 , wherein:
a height of the first fin, wherein the height of the first fin comprises a distance from a bottom of the first fin to a top of the first fin, is substantially equal to a height of the second fin, wherein the height of the second fin comprises a distance from a bottom of the second fin to a top of the second fin;
a height of the first gate portion, wherein the height of the first gate portion comprises a distance from a bottom of the first gate portion to a top of the first gate portion, is substantially equal to a height of the second gate portion, wherein the height of the second gate portion comprises a distance from a bottom of the second gate portion to a top of the second gate portion;
the top surface of the first fin is below the top surface of the second fin; and
a top surface of the first gate portion is below a top surface of the second gate portion.

5. The device of claim 2 , wherein:
a height of the first fin, wherein the height of the first fin comprises a distance from a bottom of the first fin to a top of the first fin, is substantially equal to a height of the second fin, wherein the height of the second fin comprises a distance from a bottom of the second fin to a top of the second fin;
a height of the first gate portion, wherein the height of the first gate portion comprises a distance from a bottom of the first gate portion to a top of the first gate portion, is greater than a height of the second gate portion, wherein the height of the second gate portion comprises a distance from a bottom of the second gate portion to a top of the second gate portion;
the top surface of the first fin is below the top surface of the second fin; and
a top surface of the first gate portion is at a substantially same level as a top surface of the second gate portion.

6. The device of claim 2 , wherein:
a height of the first fin, wherein the height of the first fin comprises a distance from a bottom of the first fin to a top of the first fin, is greater than a height of the second fin, wherein the height of the second fin comprises a distance from a bottom of the second fin to a top of the second fin;
a height of the first gate portion, wherein the height of the first gate portion comprises a distance from a bottom of the first gate portion to a top of the first gate portion, is greater than a height of the second gate portion, wherein the height of the second gate portion comprises a distance from a bottom of the second gate portion to a top of the second gate portion;
the top surface of the first fin is at a substantially same level as the top surface of the second fin; and
a top surface of the first gate portion is at a substantially same level as a top surface of the second gate portion.

Assignees

• Globalfoundries
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Haran Balasubramanian S
• Ponoth Shom
• Standaert Theodorus E
• Yamashita Tenko

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title