High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

Patent metadata

Field	Value
Publication number	US-9406516-B2
Application number	US-201514680078-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Sep 11, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate;
forming an interfacial layer on the substrate;
forming a high-k dielectric layer on the interfacial layer;
forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;
performing a thermal treatment;
removing the first BBM layer completely;
forming a second BBM layer on and contact the high-k dielectric layer after removing the first BBM layer completely, wherein the first BBM layer and the second BBM layer comprise same material;
forming a sacrificial layer on the second BBM layer; and
patterning the sacrificial layer to form a dummy gate.

2. The method of claim 1 , further comprising performing a pre-clean before forming the interfacial layer.

3. The method of claim 1 , further comprising:
forming a spacer on the sidewall of the dummy gate;
forming a source/drain region in the substrate adjacent to the spacer;
forming a contact etch stop layer on the dummy gates;
forming an interlayer dielectric layer (ILD) on the contact etch stop layer; and
performing a replacement metal gate (RMG) process to form the dummy gate into metal gate.

4. The method of claim 1 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.

5. The method of claim 1 , wherein the interfacial layer comprises silicon oxide.

6. The method of claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN.

7. The method of claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.

8. The method of claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.

9. The method of claim 7 , wherein the silicon layer comprises amorphous silicon.

10. The method of claim 7 , wherein the thickness of the silicon layer is between 100 Angstroms to 300 Angstroms.

11. The method of claim 1 , wherein the temperature of the thermal treatment is between 700-1000° C.

Assignees

• United Microelectronics Corp

Inventors

• Ke Jian-Cun
• Yang Chih-Wei
• Lo Kun-Yuan
• Hsu Chia-Fu
• Wang shao-wei

Classifications

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title