Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Patent metadata

Field	Value
Publication number	US-9406368-B2
Application number	US-201414159798-A
Country	US
Kind code	B2
Filing date	Jan 21, 2014
Priority date	Jan 21, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

First claim

The invention claimed is:

1. An apparatus comprising:
a memory storing data and program code;
a temperature sensor configured to determine a temperature associated with the memory; and
a controller in communication with the memory and the temperature sensor, the controller configured to:
receive the temperature;
execute the program code to determine a level of write queue utilization associated with the memory; and
perform a write operation based on the temperature and based on whether the level of write queue utilization has reached a high water mark indicator, wherein the high water mark indicator is incremented in response to receiving a first write request and decremented in response to writing a second write request to the memory.

2. The apparatus of claim 1 , further comprising a false write queue configured to generate a false write request during the write operation.

3. The apparatus of claim 1 , wherein the high water mark indicator corresponds to a threshold number of requests in the write queue.

4. The apparatus of claim 1 , wherein the controller is further configured to adjust a programming pulse width during the write operation.

5. The apparatus of claim 1 , further comprising a multiplexer configured to receive the high water mark indicator as a first input, and to receive a second input from a false write queue.

6. A non-transitory computer readable storage medium comprising instructions, that when executed by a processor, cause the processor to:
determine a temperature associated with a memory;
determine a level of write queue utilization associated with the memory; and
determine a write operation based on the temperature and based on whether the level of write queue utilization has reached a high water mark indicator, wherein the high water mark indicator is incremented in response to receiving a first write request and decremented in response to writing a second write request to the memory.

7. The apparatus of claim 1 , wherein the controller is further configured to stop false writes when the temperature associated with the memory reaches a particular temperature.

8. The apparatus of claim 1 , wherein the controller is further configured to increase the temperature associated with the memory by performing a false write operation when the level of write queue utilization is less than the high water mark indicator.

9. The apparatus of claim 1 , wherein the high water mark indicator corresponds to a programmable threshold value.

10. The apparatus of claim 1 , wherein the controller is further configured to determine that the temperature associated with the memory is less than a latency-determining threshold value.

11. The apparatus of claim 1 , wherein the controller is further configured to perform a bulk write operation that services multiple write requests.

12. A non-transitory computer readable storage medium comprising instructions, that when executed by a processor, cause the processor to:
determine a temperature associated with a memory;
determine a level of write queue utilization associated with the memory; and
determine whether to perform a false write operation based on the temperature and based on whether the level of write queue utilization has reached a high water mark indicator, wherein the high water mark indicator is incremented in response to receiving a first write request and decremented in response to writing a second write request to the memory.

13. The apparatus of claim 1 , wherein the controller is further configured to:
adjust a programming pulse width based on the temperature in response to determining that the temperature is greater than a latency-determining threshold; and
perform a bulk write operation based on the programming pulse width.

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Guo Xiaochen
• Hunter Hillery C
• Rivers Jude A
• Srinivasan Vijayalakshmi

Classifications

• A61H2003/004

  Trays · CPC title

• A61H2201/1633

  Seat (A61H2201/0149 takes precedence) · CPC title

• A61G5/1075

  tilting the whole seat backwards (tilting forwards for standing-up or sitting-down aids A61G5/14) · CPC title

• Y10T29/49826

  Assembling or joining · CPC title

• A61G5/02

  propelled by the patient or disabled person · CPC title