Memory tile access and selection patterns

Patent metadata

Field	Value
Publication number	US-9406362-B2
Application number	US-201313919758-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jun 17, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

First claim

The invention claimed is:

1. An apparatus comprising:
a plurality of memory tiles including a first memory tile, each memory tile of the plurality of memory tiles comprising an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors; and
selection circuitry including line drivers configured to select a storage component of a memory tile of the plurality of memory tiles based on a corresponding digit line conductor and a corresponding access line conductor to the storage component,
wherein the selection circuitry is configured to consecutively select two or more storage components of the first memory tile before selecting a storage component of a different memory tile of the plurality of memory tiles, and
wherein the two or more selected storage components of the first memory tile have different corresponding digit line conductors and different corresponding access line conductors.

2. The apparatus of claim 1 , wherein the two or more selected storage components of the first memory tile are non-adjacent to each other in the array of storage components of the first memory tile.

3. The apparatus of claim 1 , wherein the two or more selected storage components of the first memory tile are separated from each other by a distance such that accessing data stored to one of the two or more storage components does not disrupt successfully accessing data stored to the other storage components of the two or more storage components.

4. The apparatus of claim 3 , wherein the selection circuitry is configured to select the two or more storage components in the consecutive manner by selecting the storage components in response to consecutive clock pulses.

5. The apparatus of claim 1 , wherein the selection circuitry is further configured to select the two or more storage components of the first memory tile based at least partly on a disturb effect recovery time for the storage components of the first memory tile.

6. The apparatus of claim 1 , wherein the two or more selected storage components of the first memory tile include a first storage component, a second storage component, and a third storage component, the first storage component being separated from the second storage component by a distance and the second storage component being separated from the third storage component by the distance.

7. The apparatus of claim 1 , further comprising access circuitry configured to access the storage components of the first memory tile, wherein the selection circuitry is further configured to select the two or more storage components of the first memory tile so that consecutively accessed storage locations of the first memory tile are along a diagonal from one another in the array of storage components of the first memory tile, the two or more storage components being accessible by different access circuitry.

8. The apparatus of claim 1 , wherein the storage components comprise resistive memory elements having at least two resistive states.

9. The apparatus of claim 1 , wherein each memory tile of the plurality of memory tiles is individually addressable based on an address programmed into the selection circuitry.

10. A method of operating a memory device, the method comprising:
determining memory addresses of storage locations of a memory tile of a plurality of memory tiles, each of the memory addresses having a corresponding digit line conductor and a corresponding access line conductor, each memory tile of the plurality of memory tiles comprising an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors; and
selecting the corresponding digit line conductors and the corresponding access line conductors to the determined memory addresses of the storage locations of the memory tile to access the storage locations of the memory tile,
wherein at least two or more storage components of the memory tile are selected before selecting the storage components of a different memory tile of the plurality of memory tiles, and
wherein determining the memory addresses of the storage locations of the memory tile comprises determining a first memory address of a first storage location of the memory tile based at least partly on a second memory address of a second storage location of the memory tile, the first and second memory addresses having different corresponding digit line conductors and different corresponding access line conductors.

11. The method of claim 10 , wherein the corresponding digit line conductors and the corresponding access line conductors are selected so that accessing data stored to one of the two or more storage components does not disrupt successfully accessing data stored to the other storage components of the two or more storage components.

12. The method of claim 10 , wherein the corresponding digit line conductors and the corresponding access line conductors are selected so that two consecutively accessed storage locations of the memory tile are non-adjacent to each other in the array of storage components of the memory tile.

13. The method of claim 12 , wherein the corresponding digit line conductors and the corresponding access line conductors are selected so that consecutively accessed storage locations of the memory tile are along a diagonal from one another in the array of storage components of the memory tile, the consecutively accessed storage locations being accessible by different access circuitry configured to access the storage components of the memory tile.

Assignees

• Micron Technology Inc

Inventors

• Castro Hernan A
• Tedrow Kerry Dean
• Wu Jack Chinho

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/10 Primary

  Decoders · CPC title

• G06F13/1605 Primary

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

• G06F13/1668

  Details of memory controller · CPC title