Semiconductor wafer and method of fabricating an IC die

Patent metadata

Field	Value
Publication number	US-9406347-B2
Application number	US-201414574597-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.
There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.

First claim

The invention claimed is:

1. A semiconductor wafer comprising a plurality of replicated integrated circuit, IC, modules, each replicated IC module capable of forming an individual IC die;
wherein the semiconductor wafer further comprises inter-module cross-wafer electrical connections and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.

2. The semiconductor wafer of claim 1 , wherein the replicated IC modules are arranged into a two dimensional array layout within the semiconductor wafer of n×m replicated IC modules, where n is greater than or equal to 1, and wherein n is a first number of replicated IC modules in a first direction on the semiconductor wafer, and m is a second number of replicated IC modules in a second direction on the semiconductor wafer, wherein the first and second directions are orthogonal to each other.

3. The semiconductor wafer of claim 2 , wherein the semiconductor wafer comprises at least one inter-module cross-wafer electrical connection between each pair of adjacent replicated IC modules within the array layout.

4. The semiconductor wafer of claim 2 , wherein each replicated IC module comprises an address decoding and routing component arranged to implement a unique address range addressing scheme.

5. The semiconductor wafer of claim 1 , wherein each replicated IC module comprises at least one inter-module cross-wafer electrical connection spanning at least one scribe and edge seal boundary of the replicated IC module, and operably coupling said replicated IC module to at least one further replicated IC module.

6. The semiconductor wafer of claim 5 , wherein each replicated IC module is operably coupled to adjacent replicated IC modules on all four sides thereof by inter-module cross-wafer electrical connections.

7. The semiconductor wafer of claim 6 , wherein:
inter-module cross-wafer electrical connections provided on first sides of each replicated IC module along a first orientation and a second orientation are arranged to push accesses to memory mapped resources within adjacent replicated IC modules; and
inter-module cross-wafer electrical connections provided on second sides of each replicated IC module along the first orientation and the second orientation are arranged to receive accesses to memory mapped resources from adjacent replicated IC modules.

8. The semiconductor wafer of claim 1 , wherein the inter-module cross-wafer electrical connections comprise memory expansion interfaces.

9. The semiconductor wafer of claim 1 , wherein at least one of electrical, mechanical and logical protection is provided for the inter-module cross-wafer electrical connections.

10. The semiconductor wafer of claim 1 , wherein each replicated IC module comprises at least one external interface connection.

11. The semiconductor wafer of claim 10 , wherein the at least one external interface connection comprises a System-In-Packaging, SiP, interface connection.

12. The semiconductor wafer of claim 10 , wherein the at least one external interface connection comprises a bus slave connection arranged to be connected to an external bus master.

13. The semiconductor wafer of claim 1 , wherein the replicated IC modules comprise IC resources capable of being memory mapped.

14. The semiconductor wafer of claim 13 , wherein the replicated IC modules comprise at least one of:
memory modules;
logic circuits; and
processing blocks.

15. A set of wafer masks for fabricating a semiconductor wafer according to claim 1 .

16. An integrated circuit die from a semiconductor wafer according to claim 1 .

17. An integrated circuit device comprising at least one die from a semiconductor wafer according to claim 1 implemented within a single integrated circuit package.

18. A method of fabricating an integrated circuit, IC, die, the method comprising:
fabricating a semiconductor wafer including: plurality of replicated integrated circuit, IC, modules, each replicated IC module capable of forming an individual IC die and including edge seal boundaries, the replicated IC modules arranged to be cut into IC dies comprising multiple replicated IC modules, and inter-module cross-wafer electrical connections and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules;
determining a required configuration of replicated IC modules;
identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules; and
cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.

19. The method of claim 18 , wherein each replicated IC module comprises at least one inter-module cross-wafer electrical connection spanning at least one scribe and edge seal boundary of the replicated IC module, and operably coupling said replicated IC module to at least one further replicated IC module.

20. A semiconductor wafer comprising:
a plurality of replicated integrated circuit, IC, modules including a first replicated IC module and a second replicated IC module, each replicated IC module capable of forming an individual IC die and including edge seal boundaries, the replicated IC modules arranged to be cut into IC dies comprising multiple replicated IC modules;
a plurality of scribe line separating the replicated IC modules; and
an inter-module cross-wafer electrical connection spanning a first scribe line of the scribe lines and an edge seal boundary of the first replicated IC module and the edge seal boundary of a second replicated IC module to operably couple the first and second replicated IC modules.

Assignees

• Moran Robert F
• Beattie Derek
• Maiolani Mark
• Freescale Semiconductor Inc

Inventors

• Moran Robert F
• Beattie Derek
• Maiolani Mark

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H01L21/82

  Electricity · mapped topic