Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol

Patent metadata

Field	Value
Publication number	US-9405718-B2
Application number	US-201313976548-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Feb 28, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

First claim

What is claimed is:

1. An interconnect architecture device comprising:
a processor to generate a transaction that is not compliant with LLI;
conversion logic coupled with the processor, the conversion logic to convert the transaction, which is not compliant with LLI, to an LLI packet; and
an LLI controller coupled with the conversion logic, the LLI controller to couple the interconnect architecture device with an LLI link, the LLI controller to transmit a symbol corresponding to the LLI packet on the LLI link, wherein the transaction is selected from a PCI configuration transaction and a PCIE configuration transaction, and wherein the conversion logic is to convert the configuration transaction to an LLI service packet.

2. The device of claim 1 , wherein the conversion logic comprises logic to convert the transaction selected from a Peripheral Component Interconnect (PCI) transaction, a Peripheral Component Interconnect Express (PCIE) transaction, and a Peripheral Component Interconnect extended (PCI-X) transaction to the LLI packet.

3. The device of claim 1 , wherein the transaction is to be used for at least one of enumeration and configuration of a device that is to be coupled with the LLI link.

4. The device of claim 1 , wherein the transaction is selected from a PCI memory-mapped transaction and a PCIE memory-mapped transaction, and wherein the conversion logic is to convert the memory-mapped transaction to an LLI transaction packet.

5. The device of claim 1 , wherein the conversion logic is to provide the LLI packet to a transaction layer of an LLI stack of the LLI controller.

6. The device of claim 1 , further comprising:
a memory coupled with the processor; and
a module stored in the memory, the module selected from an enumeration module and a configuration module, wherein the module is of an interconnect protocol that is different from the LLI, and
wherein the processor is to generate the transaction in response to executing one or more instructions of the module.

7. The device of claim 1 , wherein the interconnect architecture device does not have an interconnect conforming to an interconnect protocol that the transaction is compliant with other than LLI.

8. An interconnect architecture device comprising:
an LLI controller, the LLI controller to couple the interconnect architecture device with an LLI link, the LLI controller to receive a symbol on the LLI link;
conversion logic coupled with the LLI controller, the conversion logic to convert an LLI packet corresponding to the received symbol to a transaction that is not compliant with LLI; and
logic of an interconnect protocol that is compliant with the transaction coupled with the conversion logic to service the transaction, wherein the logic that is of the interconnect protocol that is compliant with the transaction is not coupled with an interconnect that uses the interconnect protocol.

9. The device of claim 8 , wherein the conversion logic comprises logic to convert the LLI packet to a transaction selected from a PCI transaction, a PCIE transaction, and a PCI-X transaction.

10. The device of claim 8 , wherein the logic that is of the interconnect protocol that is compliant with the transaction comprises one of PCI endpoint logic and PCIE endpoint logic.

11. The device of claim 10 , wherein the logic that is of the interconnect protocol that is compliant with the transaction comprises root-complex integrated endpoint logic.

12. The device of claim 8 , wherein the transaction is to be used to at least one of configure the interconnect architecture device and enumerate the interconnect architecture device to an interconnect architecture device that is to be coupled with the LLI link.

13. The device of claim 8 , wherein the LLI packet comprises an LLI service packet, and wherein the conversion logic is to convert the LLI service packet to one of a PCI configuration transaction and a PCIE configuration transaction.

14. The device of claim 8 , wherein the LLI packet comprises an LLI transaction packet, and wherein the conversion logic is to convert the LLI transaction packet to one of a PCI memory-mapped transaction and a PCIE memory-mapped transaction.

15. An interconnect architecture device comprising:
an LLI controller, the LLI controller to couple the interconnect architecture device with an LLI link, the LLI controller to receive a symbol on the LLI link;
conversion logic coupled with the LLI controller, the conversion logic to convert an LLI packet corresponding to the received symbol to a transaction that is not compliant with LLI; and
logic of an interconnect protocol that is compliant with the transaction coupled with the conversion logic to service the transaction, wherein the conversion logic is to receive the LLI packet from a transaction layer of an LLI stack of the LLI controller, and wherein the logic that is of the interconnect protocol that is compliant with the transaction is not coupled with an interconnect that uses the interconnect protocol.

16. A method in an interconnect architecture device comprising:
generating a transaction that is of a different interconnect protocol than LLI within the interconnect architecture device;
converting the transaction, which is of the different interconnect protocol than the LLI, to an LLI packet; and
transmitting a symbol corresponding to the LLI packet on an LLI link, wherein the transaction is selected from a PCI configuration transaction and a PCIE configuration transaction, and wherein the conversion logic is to convert the configuration transaction to an LLI service packet.

17. The method of claim 16 , wherein converting comprises converting one of a PCI transaction, a PCIE transaction, and a PCI-X transaction to the LLI packet.

18. The method of claim 16 , wherein generating comprises generating the transaction as part of at least one of enumeration and configuration of an interconnect architecture device coupled with the LLI link.

19. A system comprising:
a battery;
a dipole antenna;
a memory to store a PCI based protocol module;
an LLI link;
an interconnect architecture device comprising an LLI controller to couple the interconnect architecture device with the LLI link, the LLI controller to receive a symbol on the LLI link;
conversion logic coupled with the LLI controller, the conversion logic to convert an LLI packet corresponding to the received symbol to a transaction that is not compliant with LLI; and
logic of an interconnect protocol that is compliant with the transaction coupled with the conversion logic to service the transaction, wherein the logic that is of the interconnect protocol that is compliant with the transaction is not coupled with an interconnect that uses the interconnect protocol.

20. The system of claim 19 , wherein the transactions of the PCI based protocol are to comprise at least one of transactions to enumerate the interconnect architecture device and transactions to configure the interconnect architecture device.

21. The system of claim 19 , wherein the PCI based protocol comprises PCI.

22. The system of claim 19 , wherein the PCI based protocol comprises PCIE.

Assignees

• Ranganathan Sridharan
• Wagh Mahesh
• Intel Corp

Inventors

• Ranganathan Sridharan
• Wagh Mahesh

Classifications

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F3/0661

  Format or protocol conversion arrangements · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title