Instruction and logic for adaptive dataset priorities in processor caches

Patent metadata

Field	Value
Publication number	US-9405706-B2
Application number	US-201414496255-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Sep 25, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

First claim

What is claimed is:

1. A processor, comprising:
a front end including circuitry to receive an instruction defining a priority dataset, the priority dataset including a plurality of ranges of memory addresses, each range corresponding to a respective priority level;
a cache; and
a cache controller, including circuitry to:
detect a miss in the cache for a requested cache value;
determine a candidate cache victim from the cache;
determine a priority of the requested cache value according to the priority dataset;
determine a priority of the candidate cache victim according to the priority dataset;
evict the candidate cache victim based on whether the priority of the candidate cache victim is less than or equal to the priority of the requested cache value;
maintain a first count of previous evicted cache victims with higher priority than respective previous requested cache values;
maintain a second count of previous evicted cache victims with lower or equal priority than respective previous requested cache values; and
adjust eviction policies based upon the first count and the second count.

2. The processor of claim 1 , wherein the cache controller further includes circuitry to evict the candidate cache victim further based on an instruction to adjust evaluation of the priority dataset.

3. The processor of claim 1 , wherein the cache controller further includes circuitry to, upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, search for a new candidate cache victim to compare with the requested cache value.

4. The processor of claim 1 , wherein the cache controller further includes circuitry to:
upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, search for a new candidate cache victim with a lower or equal priority to the requested cache value; and
bound the search for the new candidate cache victim with a threshold, the threshold determined from the priority of the requested cache value.

5. A method comprising, within a processor:
receiving an instruction defining a priority dataset, the priority dataset including a plurality of ranges of memory addresses, each range corresponding to a respective priority level;
detecting a miss in a cache for a requested cache value;
determining a candidate cache victim from the cache;
determining a priority of the requested cache value according to the priority dataset;
determining a priority of the candidate cache victim according to the priority dataset;
determining whether to evict the candidate cache victim based on whether the priority of the candidate cache victim is less than or equal to the priority of the requested cache value;
maintaining a first count of previous evicted cache victims with higher priority than respective previous requested cache values;
maintaining a second count of previous evicted cache victims with lower or equal priority than respective previous requested cache values; and
adjusting eviction policies based upon the first count and the second count.

6. The method of claim 5 , further comprising evicting the candidate cache victim further based on an instruction to adjust evaluation of the priority dataset.

7. The method of claim 5 , further comprising, upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, search for a new candidate cache victim to compare with the requested cache value.

8. The method of claim 5 , further comprising:
upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, searching for a new candidate cache victim with a lower or equal priority to the requested cache value; and
bonding the search for the new candidate cache victim with a threshold, the Threshold determined from the priority of the requested cache value.

9. A system for executing instructions, including:
a front end including circuitry to receive an instruction defining a priority dataset, the priority dataset including a plurality of ranges of memory addresses, each range corresponding to a respective priority level;
a cache; and
a cache controller, including circuitry to:
detect a miss in the cache for a requested cache value;
determine a candidate cache victim from the cache;
determine a priority of the requested cache value according to the priority dataset;
determine a priority of the candidate cache victim according to the priority dataset;
evict the candidate cache victim based on whether the priority of the candidate cache victim is less than or equal to the priority of the requested cache value;
maintain a first count of previous evicted cache victims with higher priority than respective previous requested cache values;
maintain a second count of previous evicted cache victims with lower or equal priority than respective previous requested cache values; and
adjust eviction policies based upon the first count and the second count.

10. The system of claim 9 , wherein the cache controller further includes circuitry to evict the candidate cache victim further based on an instruction to adjust evaluation of the priority dataset.

11. The system of claim 9 , wherein the cache controller further includes circuitry to, upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, search for a new candidate cache victim to compare with the requested cache value.

12. The system of claim 9 , wherein the cache controller further includes circuitry to:
upon a determination that the priority of the candidate cache victim is higher than the priority of the requested cache value, search for a new candidate cache victim with a lower or equal priority to the requested cache value; and
bound the search for the new candidate cache victim with a threshold, the threshold determined from the priority of the requested cache value.

Assignees

• Intel Corp

Inventors

• Doshi Kshitij A
• Raman Karthik
• Hughes Christopher J

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title