Method of operating nonvolatile memory device comprising resistance material

US9405615B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9405615-B2
Application numberUS-201414278354-A
CountryUS
Kind codeB2
Filing dateMay 15, 2014
Priority dateAug 19, 2013
Publication dateAug 2, 2016
Grant dateAug 2, 2016

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Abstract

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A method of operating a nonvolatile memory device comprises applying a read current with a first level to a nonvolatile memory cell comprising a variable resistance material, determining read data based on the applied read current, checking a syndrome corresponding to the read data to determine whether the read data is pass or fail, changing the read current from the first level to a second level, which is different from the first level, according to the determination of whether the read data is pass or fail, and performing a read-retry operation comprising applying the read current of the second level to the nonvolatile memory cell.

First claim

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What is claimed is: 1. A method of operating a nonvolatile memory device, comprising: receiving a first calibration code from a controller and determining a first read current having a first level according to the first calibration code; applying the first read current to a nonvolatile memory cell comprising a variable resistance material, and determining read data based on the applied first read current; checking a syndrome corresponding to the read data to determine whether the read data is pass or fail; changing the first read current to a second read current having a second level different from the first level in response to the determination of whether the read data is pass or fail and in response to a second calibration code from the controller; and performing a read-retry operation comprising applying the second read current to the nonvolatile memory cell. 2. The method of claim 1 , wherein changing the first read current to the second read current comprises changing a level of a constant voltage for sensing, and generating the second read current using the changed constant voltage for sensing. 3. The method of claim 1 , further comprising: generating multiple read currents having different levels and including the first read current and the second read current, before applying the first read current to the nonvolatile memory cell, wherein applying the first read current to the nonvolatile memory cell comprises selecting the first read current from among the multiple read currents, and changing the first read current to the second read current comprises selecting the second read current from among the multiple read currents. 4. The method of claim 1 , further comprising providing a result of the determination of whether the read data is pass or fail to the controller through a predetermined pin. 5. The method of claim 1 , wherein the nonvolatile memory cell is a reference memory cell, and determining the read data comprises reading reference memory cell data stored in the reference memory cell. 6. The method of claim 1 , wherein applying the first read current to the nonvolatile memory cell comprises checking a predetermined internal signal and setting the first read current to the first level in response to the internal signal. 7. The method of claim 6 , wherein the nonvolatile memory cell is a resistive memory cell or a phase change memory cell. 8. A method of operating a nonvolatile memory device, comprising: reading reference memory cell data by applying a read current with a first level to a reference memory cell; determining whether the read reference memory cell data is pass or fail; setting the level of the read current to a second level, which is different from the first level, according to a result of the determination; performing a read-retry operation on the reference memory cell by applying a read current with a second level to the reference memory cell; and where read-retried reference memory cell data is pass, applying the read current with the second level to a normal memory cell to read normal cell data. 9. The method of claim 8 , wherein the setting of the level of the read current to the second level comprises changing a level of a constant voltage for sensing according to the result of the determination, and generating the read current of the second level by using the changed constant voltage for sensing. 10. The method of claim 8 , wherein at least one of the reference memory cell and the normal memory cell is a resistive memory cell or a phase change memory cell. 11. The method of claim 8 , further comprising applying the result of the determination to a controller through a predetermined pin. 12. The method of claim 8 , wherein applying the read current with the first level to the reference memory cell comprises receiving a first calibration code from a controller, and determining a level of the read current according to the first calibration code. 13. A method of operating a nonvolatile memory device, comprising: checking a predetermined internal signal of the nonvolatile memory device; changing a level of a read current to a first level according to a result of the checking; reading data by applying the read current with the first level to a nonvolatile memory cell comprising a resistance material; determining whether the read data is pass or fail; changing the level of the read current to a second level, which is different from the first level, according to a result of the determination of whether the read data is pass or fail; and performing a read-retry operation comprising applying the read current of the second level to the nonvolatile memory cell, wherein changing the level of the read current to the second level comprises receiving a second calibration code from the controller and changing the level of the read current according to the second calibration code. 14. The method of claim 13 , wherein changing the level of the read current comprises changing a level of a constant voltage for sensing, and generating the read current with the second level using the changed constant voltage for sensing. 15. The method of claim 13 , further comprising: generating multiple read currents having different levels before applying the read current with the first level to the nonvolatile memory cell, wherein applying the read current with the first level to the nonvolatile memory cell comprises selecting a read current among the read currents and applying the selected read current to the nonvolatile memory cell, and the changing the read current to the second level comprises selecting another read current among the read currents and applying the selected another read current to the nonvolatile memory cell. 16. The method of claim 13 , further comprising providing the result of the determination of whether the read data is pass or fail to a controller through a predetermined pin. 17. The method of claim 13 , wherein applying the read current with the first level to the nonvolatile memory cell comprises receiving a first calibration code from a controller, and determining a level of the read current according to the first calibration code.

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Classifications

  • Online error correction · CPC title

  • Reading or sensing circuits or methods · CPC title

  • comprising amorphous/crystalline phase transition cells · CPC title

  • Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

  • Sensing or reading circuits; Data output circuits · CPC title

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What does patent US9405615B2 cover?
A method of operating a nonvolatile memory device comprises applying a read current with a first level to a nonvolatile memory cell comprising a variable resistance material, determining read data based on the applied read current, checking a syndrome corresponding to the read data to determine whether the read data is pass or fail, changing the read current from the first level to a second lev…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/10. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).