Prioritizing instructions based on the number of delay cycles

Patent metadata

Field	Value
Publication number	US-9405548-B2
Application number	US-201113314052-A
Country	US
Kind code	B2
Filing date	Dec 7, 2011
Priority date	Dec 7, 2011
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Methods, systems, and computer program products may provide delay-identification in data processing systems. An apparatus may include a delay-identification unit having a delay counter, a threshold register, a delay register, and a delay detector. The delay detector may be configured to start the delay counter in response to detecting that one group of instructions is delayed, and stop the delay counter in response to detecting that the one group of instructions is no longer delayed. The delay detector may additionally be configured to compare the number of cycles counted by the delay counter with a threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.

First claim

What is claimed is:

1. An apparatus, comprising:
an instruction-grouping circuit configured to organize a plurality of instructions for a computer processor into a plurality of instruction groups prior to execution;
a plurality of execution units configured to execute the plurality of instruction groups based upon cycles of a clock signal;
a delay-identification circuit including:
a delay counter that is configured to count a number of cycles occurring in a time period for a first group of instructions of the plurality of instruction groups, wherein the time period is an amount of time between when a group of instructions is ready to be dispatched to one or more execution units of the plurality of execution units and when the group of instructions has been completely executed by the one or more execution units;
a threshold register that is configured to store a threshold number of cycles that represents an undesired amount of delay within the time period;
a delay register that is configured to store at least one effective address of at least one instruction in the first group of instructions;
a delay detector circuit that is configured to:
detect when the first group of instructions is delayed in the time period;
in response to detecting that the first group of instructions is delayed, start the delay counter to count the number of cycles in the time period;
in response to detecting that the first group of instructions is no longer delayed, stop the delay counter;
compare the number of cycles counted with the threshold number of cycles; and
in response to determining the number of cycles counted is greater than the threshold number of cycles, store at least one effective address of at least one instruction of the first group of instructions; and

a group completion table that is configured to store data regarding the first group of instructions when the first group of instructions has been dispatched to the one or more execution units but has not been at least one of: completely executed by the one or more execution units and flushed from the apparatus;
wherein the delay detector circuit is further configured to:
detect when the first group of instructions is delayed from being dispatched to the one or more execution units; and
detect when the group completion table is empty for one or more cycles; and

wherein the delay-identification circuit communicates a frequency, from among at least a first frequency and a second frequency, for processing the first group of instructions via the one or more execution units in response to anticipating a delay in the first group of instructions.

2. The apparatus of claim 1 , wherein the delay detector circuit is further configured to:
reset the delay counter when the number of cycles counted by the delay counter is not greater than the threshold number of cycles;
detect when the first group of instructions is delayed from being completely executed by the one or more execution units;
detect when the first group of instructions has attained a next-to-complete status; and
in response to detecting that the first group of instructions has not attained a completed status within a number of cycles of attaining the next-to-complete status:
detect an oldest instruction in the one or more execution units that has not yet completed execution, wherein execution of the oldest instruction by one of the one or more execution units began before all other uncompleted instructions;
start the delay counter to count a number of cycles of the oldest instruction; and
stop the delay counter when execution of the oldest instruction completes.

3. The apparatus of claim 2 , wherein the delay detector circuit is further configured to, in response to detecting that the first group of instructions has not attained a completed status within a number of cycles of attaining the next-to-complete status:
detect when the number of cycles of the oldest instruction is greater than the threshold number of cycles;
in response to detecting the number of cycles of the oldest instruction is greater than the threshold number of cycles, store one effective address of the oldest instruction; and
in response to execution of the oldest instruction completing:
reset the delay counter; and
detect, a next oldest instruction in the first group of instructions that has not yet completed execution, wherein execution of the next oldest instruction by one of the one or more execution units began before all other uncompleted instructions.

4. The apparatus of claim 1 , wherein the delay detector circuit is further configured to:
in response to detecting the group completion table is empty for the one or more cycles, start the delay counter.

5. The apparatus of claim 4 , wherein the delay detector circuit is further configured to:
in response to detecting the group completion table is no longer empty, stop the delay counter.

6. The apparatus of claim 1 , further comprising:
a delay table that is configured to store data regarding the first group of instructions;
wherein the delay detector circuit is further configured to store, in the delay table, the number of cycles, the threshold number of cycles, and the at least one effective address.

7. The apparatus of claim 6 , further comprising:
a prioritization circuit that is configured to:
order a group of incoming instructions prior to execution by the one or more execution units;
read the delay table;
identify, within the group of incoming instructions, one or more instructions that are identified within the delay table as previously causing a delay having an associated cycle count that is greater than the threshold number of cycles;
decrease a priority of the identified one or more instructions;
fetch data needed to avoid the delay when executing the identified one or more instructions; and
in response to fetching data needed to avoid the delay, increase the priority of the identified one or more instructions.

8. The apparatus of claim 6 , further comprising a prioritization circuit that is configured to:
order a group of incoming instructions prior to execution;
read the delay table;
identify, within the group of incoming instructions, one or more instructions that are identified within the delay table as previously causing a delay having an associated cycle count that is greater than the threshold number of cycles; and
in response to identifying the one or more instructions, flush the identified one or more instructions from the apparatus.

9. The apparatus of claim 1 , wherein the plurality of execution units are configured to operate at the first frequency when the first group of instructions does not include a delay in the time period, and the second frequency that is lower than the first frequency when the first group of instructions includes a delay in the time period.

10. A method, comprising:
in response to anticipating a delay in a group of instructions, communicating a frequency by a delay-identifying apparatus from among at least a first frequency and a second frequency, for processing the group of instructions via one or more execution units;
counting, by the delay-identifying apparatus, a number of cycles of a clock signal occurring in a time period in which the group of instructions is delayed, wherein the time period is the amount of time between when the group of instructions is ready to be dispatched for execution by the one or more execution units and when the group of instructions is completely executed by the one or more execution units and is thus no longer delayed;
detecting when the group of instructions is delayed in the time period;
comparing, by the delay-identifying apparatus, the counted

Assignees

• Indukuru Venkat R
• Mericas Alexander E
• IBM

Inventors

• Indukuru Venkat R
• Mericas Alexander E

Classifications

• G06F9/3857

  Physics · mapped topic

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3853 Primary

  of compound instructions · CPC title

• G06F9/3854

  Instruction completion, e.g. retiring, committing or graduating · CPC title

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title