Signal processing unit employing a blind channel estimation algorithm and method of operating a receiver apparatus

Patent metadata

Field	Value
Publication number	US-9401826-B2
Application number	US-201313755776-A
Country	US
Kind code	B2
Filing date	Jan 31, 2013
Priority date	Feb 17, 2012
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A receiver apparatus receives a transmit signal through a plurality of transmission channels, wherein each transmission channel is described by its channel vector. A sparseness evaluation unit ( 127 ) may obtain a sparseness measure containing sparseness information for previously estimated frequency-domain channel vectors. From the plurality of receive signals, an estimator unit ( 120 ) estimates updated channel vectors for the transmission channels by applying an iterative blind channel estimation algorithm that may consider a change of the sparseness measure, out-of-band energy information and/or signal-to-noise information and cross-relations between pairs of receive signals. A combining unit ( 130 ) may combine the receive signals on the basis of combining coefficients derived from the estimated channel impulse responses for a pre-selected diversity combining scheme to obtain a combined receive signal representing an estimation of the transmit signal. The receiver apparatus employs an improved blind channel estimation approach.

First claim

The invention claimed is:

1. A signal processor comprising:
circuitry configured to
receive a plurality of receive signals, and
estimate, from the plurality of receive signals, frequency-domain channel vectors of transmission channels based on an iterative blind channel estimation algorithm, which exploits cross-relations between pairs of the receive signals and which is modified by a term considering a change in a sparseness measure obtained from the estimated frequency-domain channel vectors,
wherein each said receive signal is assigned to another one of the transmission channels and originates from a same transmit signal.

2. The signal processor of claim 1 , wherein
the circuitry is further configured to combine the receive signals based on combining coefficients derived from the estimated frequency-domain channel vectors to obtain a combined receive signal representing an estimation of the transmit signal transmitted through the transmission channels.

3. The signal processor of claim 2 , wherein
the circuitry is further configured to apply maximum ratio combining by determining, from the estimated frequency-domain channel vectors or time-domain channel impulse response vectors derived therefrom, filter coefficients for matched filters, each said matched filter matching with the estimated time-domain channel impulse response of one of the transmission channels.

4. The signal processor of claim 1 ,
wherein the circuitry is further configured to estimate the frequency-domain channel vectors based on an iterative algorithm that minimizes a cost function, and
wherein the iterative algorithm updates the frequency-domain channel vectors based on previous frequency-domain channel vectors, a predefined step size parameter, a current block error sequence vector and a current sparseness measure indicating a change in sparseness in the estimated channel vectors.

5. The signal processor of claim 4 , wherein
the current block error sequence vector represents a Fourier-transformed of block error signals between pairs of the receive signals, each said block error signal resulting from a deviation between a result of a convolution of one of the receive signals received through a first transmission channel with an estimated impulse response of a second transmission channel and a result of a convolution of another of the receive signals received through the second transmission channel with an estimated impulse response of the first transmission channel, the iterative algorithm using second-order cross-correlation information about the pairs of the receive signals.

6. The signal processor of claim 1 , wherein the circuitry is further configured to
obtain the sparseness measure, which contains sparseness information for the estimated frequency-domain channel vectors, and
adjust the estimated frequency-domain channel vectors based on an adjustment term containing the obtained sparseness measure.

7. The signal processor of claim 4 , wherein
the iterative algorithm adjusts the updated estimated frequency-domain channel vectors to increase the sparseness measure.

8. The signal processor of claim 4 , wherein
the iterative algorithm adjusts the updated estimated frequency-domain channel vectors based on an averaged time derivative of the sparseness measure.

9. The signal processor of claim 4 , wherein
the iterative algorithm adjusts the updated estimated frequency-domain channel vectors such that for each said frequency-domain channel vector a sum of channel coefficients is minimized and a signal energy for each said frequency-domain channel vector is maintained.

10. The signal processor of claim 4 , wherein
the circuitry is further configured to output Signal-to-Noise Ratio (SNR) information descriptive for current signal-to-noise ratio values of the transmission channels based on the values of the cost function.

11. The signal processor of claim 10 , wherein
the circuitry is further configured to adjust a predefined step size parameter based on the values of the cost function.

12. The signal processor of claim 11 , wherein
the circuitry is further configured to
detect, based on the frequency-domain channel vectors, a misconvergence behavior of the iterative blind channel estimation algorithm or an excess condition for out-of-band energy in a frequency range between an upper frequency limit of the receive signal and a sample frequency, and
output a control signal indicating the misconvergence behavior or the excess condition.

13. The signal processor of claim 12 ,
wherein the circuitry is further configured to limit a signal energy in frequency band edge areas of the estimated frequency-domain channel vectors in response to the control signal, and
wherein the iterative blind channel estimation algorithm proceeds with the energy-limited estimated frequency-domain channel vectors.

14. The signal processor of claim 1 , wherein
the circuitry is further configured to
measure a coherence bandwidth of the estimated frequency-domain channel vectors, and
adjust an observation window length for the iterative blind channel estimation algorithm based on the measured coherence bandwidths.

15. The signal processor of claim 14 , wherein
the circuitry is further configured to
increase the observation window length when the measured coherence bandwidth is limited by the observation window, and
decrease the observation window length when the measured coherence bandwidth is larger than the observation window allows.

16. The signal processor of claim 14 , wherein
the circuitry is further configured to
measure a channel coherence time based on previous estimated frequency-domain channel vectors, and
adjust the observation window length based on the measured channel coherence time.

17. The signal processor of claim 16 , wherein
the circuitry is further configured to
decrease the observation window length when the measured channel coherence time appears to be shorter than the observation window, and
increase the observation window length when the measured channel coherence time appears to be larger than the observation window.

18. An integrated circuit comprising the signal processor according to claim 1 .

19. An electronic device comprising:
the signal processor according to claim 1 ; and
a plurality of tuner circuits, each said tuner circuit being configured to tune to a carrier frequency of the transmission signal and to output an analog receive signal,
wherein each said analog receive signal is assigned to one of the transmission channels.

20. A method of operating a receiver apparatus, the method comprising:
obtaining, based on previous estimated frequency-domain channel vectors, a sparseness measure containing information descriptive for a sparseness of the previous estimated frequency-domain channel vectors using circuitry of the receiver apparatus; and
estimating, using the circuitry of the receiver apparatus, from a plurality of receive signals, current frequency-domain channel vectors of transmission channels based on an iterative blind channel estimation algorithm exploiting cross-relations between pairs of the receive signals,
wherein the iterative blind channel estimation algorithm is modified based on a change of the sparseness measure obtained from the estimated frequency-domain channel vectors, and
wherein each said receive signal is assigned to another one of the transmission channels and originates from a same transmit signal.

21. The method according to

Assignees

• Sony Corp

Inventors

• Eitel Ben
• Zinsser Julian
• Ahmed Salem Rana
• Uhlich Stefan

Classifications

• H04L25/025

  using least-mean-square [LMS] method · CPC title

• H04L25/0238 Primary

  using blind estimation · CPC title

• H04L25/0206

  Electricity · mapped topic

• H04L25/0204

  of multiple channels · CPC title