Wireless communication link using near field coupling

Patent metadata

Field	Value
Publication number	US-9401745-B1
Application number	US-63596109-A
Country	US
Kind code	B1
Filing date	Dec 11, 2009
Priority date	Dec 11, 2009
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.

First claim

What is claimed is:

1. A method comprising:
enabling a memory integrated circuit to communicate wirelessly with a first neighboring memory integrated circuit over a first frequency, wherein the memory integrated circuit includes a physical electrical connection to the first neighboring memory integrated circuit, wherein the physical electrical connection provides signals other than those provided wirelessly, wherein the memory integrated circuit includes:
a substrate having an upper surface and a lower surface opposite to and distinct from the upper surface;
a first loop antenna on the upper surface;
a second loop antenna on the lower surface;
a third loop antenna formed within the substrate parallel and adjacent to an edge of the substrate;
wherein a portion of the third antenna extends over the upper surface and is coupled to a portion of the third antenna within the substrate by a first via and a second via extending through the substrate; and
a plurality of connectors coupled to the lower surface;
coupling an integrated circuit chip to the upper surface within a perimeter defined by the first antenna, wherein the integrated circuit chip is configured to tune frequencies of the first, second, or third antennas;
coupling at least one of the first, second, or third antenna of the memory integrated circuit to an antenna of the first neighboring memory integrated circuit, wherein the at least one antenna is within a near field region of the antenna of the first neighboring memory integrated circuit to reduce interference from other antennas, wherein the at least one antenna is coupled to the memory integrated circuit by wire bonds;
enabling the memory integrated circuit to communicate wirelessly with a second neighboring memory integrated circuit over a second frequency; and
coupling at least one of the first, second, or third antenna of the memory integrated circuit to an antenna of the second neighboring memory integrated circuit, wherein the at least one antenna is within the near field region of the antenna second neighboring memory integrated circuit to reduce interference from other antennas, wherein the at least one antenna coupled to the antenna of the second neighboring memory integrated circuit is different than the at least one antenna coupled to the antenna of the first neighboring memory integrated circuit.

2. The method of claim 1 , further comprising forming at least one array of memory integrated circuits arranged generally in a plane.

3. The method of claim 2 , further comprising arranging at least three of the at least one memory integrated circuit arrays in parallel planes, wherein each memory integrated circuit of each of the at least three memory integrated circuit arrays is configured to communicate wirelessly with each neighboring memory integrated circuit, wherein each neighboring memory integrated circuit communicates at a different frequency, wherein antennas of each neighboring memory integrated circuit configured to communicate wirelessly are in parallel planes.

4. The method of claim 3 , further comprising forming physical electrical connections between neighboring memory integrated circuits of each of the at least three memory integrated circuit arrays.

5. The method of claim 1 , further comprising forming an array of memory integrated circuits spaced from one another at a distance of approximately one millimeter.

6. The method of claim 1 , further comprising forming a plurality of memory integrated circuits, each of the plurality of memory integrated circuits having a corresponding length and corresponding width, wherein a distance between adjacent memory integrated circuits is less than the corresponding length and the corresponding width of either of the adjacent memory integrated circuits.

7. The method of claim 1 , further comprising providing at least one of a power signal or a reference signal from the memory integrated circuit to the first neighboring memory integrated circuit via the physical electrical connection.

8. The method of claim 1 , further comprising:
coupling the integrated circuit chip to the first, second, or third antennas by wire bonds.

9. The method of claim 8 , further comprising tuning the first, second, or third antennas to different frequencies.

10. The method of claim 1 , wherein forming the first antenna includes plating of a conductive strip on the upper surface.

11. An apparatus comprising:
a substrate having an upper surface, a lower surface different from the upper surface, a first short edge, a second short edge, a first long edge, and a second long edge, wherein the edges define a perimeter of the substrate;
a first loop antenna on the upper surface and configured to couple to an antenna of a first memory integrated circuit adjacent to the upper surface;
a second loop antenna on the lower surface and configured to couple to an antenna of a second memory integrated circuit adjacent to the lower surface;
a third loop antenna formed within the substrate parallel to the first short edge and configured to couple to an antenna of a third memory integrated circuit adjacent to the first short edge;
a fourth loop antenna formed within the substrate parallel to the second short edge and configured to couple to an antenna of a fourth memory integrated circuit adjacent to the second short edge;
a fifth loop antenna formed within the substrate parallel to the first long edge and configured to couple to an antenna of a fifth memory integrated circuit adjacent to the first long edge;
a sixth loop antenna formed within the substrate parallel to the second long edge and configured to couple to an antenna of a sixth memory integrated circuit adjacent to the second long edge;
wherein a portion of each of the third, fourth, fifth, and sixth loop antennas extend over the upper surface and is coupled to a respective portion of the third, fourth, fifth, and sixth loop antennas within the substrate by a plurality of vias extending through the substrate;
a plurality of connectors coupled to the lower surface; and
an integrated circuit chip coupled to the upper surface within a perimeter defined by the first loop antenna, wherein the integrated circuit chip is further coupled to the first, second, third, fourth, fifth, and sixth loop antennas by wire bonds, wherein the integrated circuit chip is configured to tune frequencies of the loop antennas.

12. The apparatus of claim 11 , wherein the integrated circuit chip includes a control and power amplifier coupled to a first and a second capacitor, wherein the first and second capacitor are coupled in parallel, wherein the second capacitor is tunable.

13. The apparatus of claim 11 , wherein the first loop antenna is configured to couple to an additional loop antenna parallel to the first loop antenna, wherein the additional loop antenna is on a lower surface of the first memory integrated circuit positioned above the apparatus.

14. The apparatus of claim 11 , wherein the first loop antenna is a plating of a conductive strip on the upper surface.

15. The apparatus of claim 11 , wherein the apparatus is included in an array of apparatuses coupled by wire bonds, wherein the apparatuses are further configured to pass signals by electromagnetic radiation through loop antennas, wherein the loop antennas are in parallel planes, wherein the wire bonds provide signals between the apparatuses other than those provided by electromagnetic radiation.

16. The apparatus of claim 15 , wherein the array of apparatuses is a three dimensional array.

17. The apparatus of claim 15 , wherein the

Assignees

• Abdulla Mostafa Naguib
• Micron Technology Inc

Inventors

• Abdulla Mostafa Naguib

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W44/248

  for antennas · CPC title