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Semiconductor devices including gate pattern, multi-channel active pattern and diffusion layer
US9401428B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9401428-B2 |
| Application number | US-201313795778-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 12, 2013 |
| Priority date | Feb 4, 2013 |
| Publication date | Jul 26, 2016 |
| Grant date | Jul 26, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a gate pattern on a substrate, the gate pattern including a gate insulation layer; multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern; a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration; and…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/62Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9401428B2 cover?
- A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentrat…
- Who is the assignee on this patent?
- Choi Kyung-In, Kim Gyeom, Yoon Hong-Sik, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/62. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).