Semiconductor structure and method for manufacturing the same

US9401425B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9401425-B2
Application numberUS-201214437755-A
CountryUS
Kind codeB2
Filing dateNov 27, 2012
Priority dateOct 26, 2012
Publication dateJul 26, 2016
Grant dateJul 26, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate ( 130 ), a support structure ( 131 ), a base region ( 100 ), a gate stack, a spacer ( 240 ), and a source/drain region, wherein the gate stack is located on the base region ( 100 ), and the base region ( 100 ) is supported on the substrate ( 130 ) by the support structure ( 131 ), wherein the sidewall cross-section of the support structure ( 131 ) is in a shape of a concave curve; an isolation structure ( 123 ) is formed beneath the edges on both sides of the base region ( 100 ), wherein a portion of the isolation structure ( 123 ) is connected to the substrate ( 130 ); a cavity ( 112 ) is formed between the isolation structure ( 123 ) and the support structure ( 131 ); and there exists a source/drain region at least on both sides of the base region ( 100 ) and the isolation structure ( 123 ). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor structure, comprising a substrate ( 130 ), a support structure ( 131 ), a base region ( 100 ), a gate stack, a spacer ( 240 ) and a source/drain region, wherein the gate stack is located on the base region ( 100 ), and the base region ( 100 ) is supported on the substrate ( 130 ) by the support structure ( 131 ), wherein: the sidewall cross-section of the support structure ( 131 ) is in a shape of concave curve; an isolation structure…

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What does patent US9401425B2 cover?
A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate ( 130 ), a support structure ( 131 ), a base region ( 100 ), a gate stack, a spacer ( 240 ), and a source/drain region, wherein the gate stack is located on the base region ( 100 ), and the base region ( 100 ) is supported on the substrate ( 130 ) by the support structure ( 131 ), wherein the sidewall cro…
Who is the assignee on this patent?
Inst Of Microelectronics Cas
What technology area does this patent fall under?
Primary CPC classification H10D84/0128. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).