Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9401395-B2
Application number	US-201615017059-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Aug 12, 2011
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

First claim

What is claimed is:

1. A device comprising:
an interposer, the interposer comprising:
a substrate;
a first metallization layer over the substrate and a second metallization layer over the first metallization layer;
a capacitor in the second metallization layer, the capacitor comprising a bottom electrode, a dielectric over the bottom electrode, and a top electrode over the dielectric; and

a first contact pad electrically coupled to the bottom electrode; and
an integrated circuit die, wherein the capacitor is electrically coupled between the integrated circuit die and the first contact pad.

2. The device of claim 1 , wherein the interposer further comprises a through via, wherein the capacitor is electrically coupled between the integrated circuit die and the through via.

3. The device of claim 1 , further comprising a first via layer interposed between the first metallization layer and the second metallization layer.

4. The device of claim 3 , wherein the bottom electrode extends through the first via layer.

5. The device of claim 4 , further comprising a conductive interconnect, the conductive interconnect comprising a first conductive line in the second metallization layer and a first conductive via extending through the first via layer.

6. The device of claim 1 , further comprising a top plate pick-up, wherein the top plate pick-up extends into the second metallization layer.

7. The device of claim 1 , wherein the interposer is free of active devices.

8. A device comprising:
an interposer substrate;
a first dielectric layer over the interposer substrate;
a second dielectric layer over the first dielectric layer;
a first electrode in the second dielectric layer and extending through the first dielectric layer;
a capacitor dielectric over the first electrode in the first dielectric layer and the second dielectric layer;
a second electrode over the capacitor dielectric in the first dielectric layer and the second dielectric layer;
a first via extending through the first dielectric layer;
a first conductive line extending through the second dielectric layer, the first conductive line coupled to the first via; and
an integrated circuit die electrically coupled to the first conductive line, the first conductive line being interposed between the integrated circuit die and the interposer substrate.

9. The device of claim 8 , wherein the first electrode does not extend to an upper surface of the second dielectric layer.

10. The device of claim 8 , wherein the second electrode extends over a top surface of the second dielectric layer.

11. The device of claim 10 , further comprising a top plate pickup in the second dielectric layer.

12. The device of claim 11 , wherein the second electrode extends laterally over the second dielectric layer to the top plate pickup.

13. The device of claim 8 , wherein an upper surface of the second dielectric layer is level with an upper surface of the second electrode and the capacitor dielectric.

14. The device of claim 13 , wherein the upper surface of the second dielectric layer is level with an upper surface of the first electrode.

15. The device of claim 8 , wherein the second electrode comprises a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer completely fills an area interposed between opposing sidewalls of the capacitor dielectric.

16. The device of claim 8 , further comprising a third dielectric layer over the second electrode, wherein the third dielectric layer extends into the second dielectric layer.

17. A device comprising:
an interposer, the interposer comprising:
an interposer substrate;
a plurality of dielectric layers on a first side of the interposer substrate;
contact pads on a second side of the interposer substrate;
a capacitor extending through at least a first dielectric layer and a second dielectric layer of the plurality of dielectric layers; and
an interconnect extending through the first dielectric layer and the second dielectric layer, the interconnect comprising a via extending through the first dielectric layer and a conductive line extending through the second dielectric layer.

18. The device of claim 17 , wherein the capacitor comprises:
a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer, the first electrode not extending to an upper surface of the second dielectric layer;
a capacitor dielectric layer over the first electrode, the capacitor dielectric layer extending to the upper surface of the second dielectric layer; and
a second electrode over the capacitor dielectric layer, the second electrode extending to the upper surface of the second dielectric layer.

19. The device of claim 17 , wherein the capacitor comprises:
a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer;
a capacitor dielectric layer over the first electrode; and
a second electrode over the capacitor dielectric layer, upper surfaces of the first electrode, the capacitor dielectric layer, and the second electrode being level with an upper surface of the second dielectric layer.

20. The device of claim 17 , wherein the capacitor comprises:
a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer;
a capacitor dielectric layer over the first electrode, the capacitor dielectric layer extending over an upper surface of the second dielectric layer; and
a second electrode over the capacitor dielectric layer, the second electrode extending over an upper surface of the second dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tzeng Kuo-Chyuan
• Tu Kuo-Chi
• Wang Chen-Jong
• Lee Hsiang-Fan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title