Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9401386-B2
Application number	US-201514878434-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Apr 25, 2013
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A semiconductor memory device includes a semiconductor substrate including a plane portion expanding in a first direction and a second direction perpendicular to the first direction, and a pillar portion formed on an upper surface of the plane portion and extending in a stacking direction, a first gate electrode formed on a first gate insulating layer on a lower side surface of the pillar portion, and extending in the first direction, a second gate electrode formed on a second gate insulating layer on an upper side surface of the pillar portion, and extending in the second direction, a variable-resistance element formed on an upper surface of the pillar portion, and an interconnection formed on an upper surface of the variable-resistance element.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor substrate including a plane portion expanding in a first direction and a second direction perpendicular to the first direction, a fin portion formed on an upper surface of the plane portion and expanding in the first direction and a stacking direction, and a pillar portion formed on an upper surface of the fin portion and extending in the stacking direction;
a first gate electrode formed on a first gate insulating layer on a side surface of the fin portion, and extending in the first direction;
a second gate electrode formed on a second gate insulating layer on a side surface of the pillar portion, and extending in the second direction;
a variable-resistance element formed on an upper surface of the pillar portion; and
an interconnection formed on an upper surface of the variable-resistance element.

2. The device of claim 1 , wherein the variable-resistance element comprises:
a storage layer as a ferromagnetic layer having a variable magnetization direction;
a reference layer as a ferromagnetic layer having an invariable magnetization direction; and
a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer.

3. The device of claim 1 , wherein the fin portion, the first gate insulating layer, and the first gate electrode form a first selection transistor, and the pillar portion, the second gate insulating layer, and the second gate electrode form a second selection transistor.

4. The device of claim 3 , wherein when performing various operations on the variable-resistance element, a potential difference is produced between the plane portion and the interconnection while the first selection transistor and the second selection transistor are turned on.

5. The device of claim 1 , further comprising an insulating layer formed between the first gate electrode and the plane portion.

6. The device of claim 1 , further comprising an insulating layer formed between the second gate electrode and the first gate electrode.

7. The device of claim 1 , further comprising an epitaxial layer formed between the pillar portion and the variable-resistance element, and having a planar area larger than those of the pillar portion and the variable-resistance element.

8. The device of claim 1 , wherein the interconnection extends in the first direction.

9. The device of claim 1 , wherein the interconnection expands in the first direction and the second direction.

Assignees

• Nakatsuka Keisuke
• Toshiba Kk

Inventors

• Nakatsuka Keisuke

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659 Primary

  Cell access · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title