Non-volatile memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9401370-B2
Application number	US-201213607243-A
Country	US
Kind code	B2
Filing date	Sep 7, 2012
Priority date	Dec 21, 2011
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate are disposed on sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a channel structure formed over a substrate and including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked along a vertical direction perpendicular to the substrate, wherein the channel structure extends along a first horizontal direction parallel to the substrate and has a first sidewall and a second sidewall;
memory cells sharing each of the channel layers and arranged along the first horizontal direction to form a string; a first selection gate electrode and a second selection gate electrode that are disposed on the first sidewall and the second sidewall of the channel structure, respectively, and are conductive, wherein the first selection gate electrode and the second selection gate electrode are located at a same level in the vertical direction and located at a same end of the string in the first horizontal direction; and
an insulation layer interposed between the first selection gate electrode and the channel structure, and between the second selection gate electrode and the channel structure,
wherein a work function of the first selection gate electrode is different from a work function of the second selection gate electrode so that the work function of the first selection gate electrode and the work function of the second selection gate electrode are located at a same point along the channel structure with respect to a line normal to the sidewalls of the channel structure, and
the first selection gate electrode, each of the channel layers and the insulation layer interposed therebetween form a first selection transistor, and the second selection gate electrode, each of the channel layers and the insulation layer interposed therebetween form a second selection transistor.

2. The non-volatile memory device of claim 1 , wherein the first selection gate electrode is formed of a semiconductor material having a first conductive type, and the second selection gate electrode is formed of a semiconductor material having a second conductive type that is different from the first conductive type.

3. The non-volatile memory device of claim 2 , wherein the first selection gate electrode is formed of N-type polysilicon, and the second selection gate electrode is formed of P-type polysilicon.

4. The non-volatile memory device of claim 1 , wherein the channel structure includes a plurality of channel structures, and
the first selection gate electrode and the second selection gate electrode are alternately arrayed along a horizontal direction parallel to the substrate, between the channel structures.

5. The non-volatile memory device of claim 1 , further comprising:
an extended portion disposed over or under the channel structure, extending in a first direction crossing the channel structure and coupled with the first selection gate and the second selection gate.

6. The non-volatile memory device of claim 1 , further comprising:
a first extended portion disposed over the channel structure, extending in a first direction crossing the channel structure and coupled with the first selection gate electrode, and
a second extended portion disposed under the channel structure, extending in the first direction and coupled with the second selection gate electrode.

7. The non-volatile memory device of claim 6 , wherein the first extended portion is formed of a same material as a material forming the first selection gate electrode, and
the second extended portion is formed of a same material as a material forming the second selection gate electrode.

8. The non-volatile memory device of claim 1 , wherein a Gate-Induced Drain Leakage (GIDL) current generated according to a voltage applied to the first selection gate electrode and the second selection gate electrode is used in an erase operation mode.

Assignees

• Choi Sang-Moo
• Park Byung-Soo
• Oh Sang-Hyun
• Joo Han-Soo
• Sk Hynix Inc

Inventors

• Choi Sang-Moo
• Park Byung-Soo
• Oh Sang-Hyun
• Joo Han-Soo

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic