Stack of integrated-circuit chips and electronic device

Patent metadata

Field	Value
Publication number	US-9401349-B2
Application number	US-201514723893-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Jun 12, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.

First claim

What is claimed is:

1. A stack of integrated-circuit chips, comprising:
a first and a second integrated-circuit chip having opposing first and second faces, respectively, located at a distance from one another;
a spacer interposed between a part of a peripheral region of the second face of the second chip and the first face of the first chip, the spacer being vertically aligned with the first face of the first chip and the part of the peripheral region of the second face of the second chip;
a first adhesive attaching the spacer only to one of the first and second faces; and
a second adhesive interposed between a central region of the second face of the second chip and the first face of the first chip in order to fasten the first and second integrated-circuit chips to one another;
wherein the second adhesive is separated from and not in contact with the spacer.

2. The stack according to claim 1 , further comprising electrical connection wires connected between the first and second chips.

3. The stack according to claim 1 , wherein the spacer forms at least one vent from said central region.

4. The stack according to claim 1 , wherein the spacer comprises a spacing ring.

5. The stack according to claim 4 , wherein the spacing ring comprises at least one groove forming a vent from said central region.

6. The stack according to claim 1 , wherein the spacer comprises an open spacing ring.

7. The stack according to claim 1 , wherein the spacer comprises a plurality of pillars separated from one another, each pillar being fastened by said first adhesive to only one of the first and second faces.

8. The stack according to claim 1 , wherein the second adhesive comprises at least one drop of adhesive material.

9. The stack according to claim 1 , wherein the second integrated-circuit chip comprises a pressure sensor.

10. The stack according to claim 1 , further comprising an encapsulation package having at least one through-opening.

11. The stack according to claim 10 , wherein the encapsulation package is at least partially filled with a gel.

12. An apparatus, comprising:
a first integrated-circuit chip having a top surface;
a second integrated-circuit chip having a bottom surface;
wherein the top surface faces the bottom surface;
a spacer positioned between the top surface and the bottom surface, the spacer being vertically aligned with the top surface and the bottom surface;
wherein said spacer is permanently attached to only one of the top and bottom surfaces;
an adhesive material configured to solely contact the top and bottom surfaces for the purpose of permanently attaching the first integrated-circuit chip to the second integrated-circuit chip.

13. The apparatus of claim 12 , wherein if said spacers is permanently attached to the top surface, said bottom surface is not permanently attached to the spacer.

14. The apparatus of claim 12 , wherein said spacer is a spacer ring.

15. The apparatus of claim 14 , wherein said spacer ring includes a vent slot.

16. The apparatus of claim 12 , further including a support substrate, wherein said first integrated-circuit chip is mounted and electrically connected to the support substrate.

17. The apparatus of claim 16 , wherein said second integrated integrated-circuit chip is electrically connected to the first integrated-circuit chip.

18. The apparatus of claim 12 , wherein said spacer comprises a plurality of spacing pillars.

19. A stack, comprising:
a first and a second integrated-circuit chip having opposing first and second faces;
a spacer interposed between the second face of the second chip and the first face of the first chip;
an adhesive for fastening the second face of the second chip to the first face of the first chip without the adhesive making contact to said spacer;
wherein the spacer is in direct contact with, but not attached to, one of the first and second faces and the spacer is attached to the other of the first and second faces.

20. The stack of claim 19 , further comprising a further adhesive configured to attach the spacer to the other of the first and second faces.

Assignees

• Stmicroelectronics (Grenoble 2) Sas
• Stmicroelectronics (Malta) Ltd
• St Microelectronics Srl

Inventors

• Crobu Angelo
• Fonk Kenneth
• Coffy Romain

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title