Semiconductor device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9401335-B2
Application number	US-201414173457-A
Country	US
Kind code	B2
Filing date	Feb 5, 2014
Priority date	Feb 20, 2013
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a connection terminal, and a guard ring that is provided on a peripheral region. In the semiconductor device, the guard ring includes a plurality of wiring layers, and a wiring layer included in the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a wiring layer of the connection terminal.

First claim

What is claimed is:

1. A semiconductor device that is connected to a wiring substrate comprising:
a semiconductor substrate having an outer edge;
a circuit provided on a circuit formation region of the semiconductor substrate;
a connection terminal that is connected to a conductive pattern included in the wiring substrate and is provided on the circuit formation region; and
a guard ring that includes a plurality of wiring layers and is provided on a peripheral region which is a region between the circuit formation region and the outer edge,
wherein the guard ring is provided on a connection region, which overlaps with the wiring substrate, and
in the connection region, a first wiring layer of the plurality of wiring layers of the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a second wiring layer of the connection terminal, the second wiring layer of the connection terminal being farther from the semiconductor substrate than a first wiring layer of the connection terminal.

2. The semiconductor device according to claim 1 , further comprising a power supply unit for supplying a predetermined potential to the semiconductor substrate,
wherein the guard ring is connected to the semiconductor substrate.

3. The semiconductor device according to claim 2 ,
wherein the semiconductor substrate includes an impurity injection layer, and
the guard ring is connected to the impurity injection layer of the semiconductor substrate.

4. An electronic apparatus comprising the semiconductor device according to claim 3 .

5. The semiconductor device according to claim 2 ,
wherein the semiconductor substrate includes:
a first impurity diffusion layer, and
a second impurity diffusion layer,

the power supply unit is connected to the first impurity diffusion layer, and
the guard ring is connected to the second impurity diffusion layer.

6. An electronic apparatus comprising the semiconductor device according to claim 2 .

7. An electronic apparatus comprising the semiconductor device according to claim 5 .

8. The semiconductor device according to claim 1 ,
wherein a third wiring layer included in the guard ring, which is the farthest from the semiconductor substrate, is provided on the same layer as the second wiring layer in a part or the entire of the peripheral region excluding the connection region.

9. An electronic apparatus comprising the semiconductor device according to claim 8 .

10. The semiconductor device according to claim 1 ,
wherein the guard ring includes a contact plug that electrically connects a first one of the plurality of wiring layers to a second of the plurality of wiring layers.

11. An electronic apparatus comprising the semiconductor device according to claim 10 .

12. The semiconductor device according to claim 1 ,
wherein the circuit includes a pixel circuit for displaying an image or a sensor circuit for capturing an image.

13. An electronic apparatus comprising the semiconductor device according to claim 12 .

14. An electronic apparatus comprising the semiconductor device according to claim 1 .

15. A semiconductor device that is connected to a wiring substrate comprising:
a substrate having an outer edge;
a circuit provided on a circuit formation region of the substrate;
a power supply unit for supplying a predetermined potential and is provided on the circuit formation region;
a connection terminal that is connected to a conductive pattern included in the wiring substrate and is provided on the circuit formation region; and
a guard ring that includes a plurality of wiring layers and is provided on the peripheral region which is a region between the circuit formation region and the outer edge,
wherein the predetermined potential is supplied to the guard ring from the power supply unit,
wherein the guard ring is provided on a connection region, which overlaps with the wiring substrate, and
in the connection region, a first wiring layer of the plurality of wiring layers of the guard ring, which is the farthest from the semiconductor substrate, corresponds to a wiring layer closer to the semiconductor substrate relative to a second wiring layer of the connection terminal, the second wiring layer of the connection terminal being farther from the semiconductor substrate than a first wiring layer of the connection terminal.

16. The semiconductor device according to claim 15 ,
wherein the guard ring is connected to the substrate.

17. An electronic apparatus comprising the semiconductor device according to claim 16 .

18. The semiconductor device according to claim 15 ,
wherein a third wiring layer included in the guard ring, which is the farthest from the substrate, is provided on the same layer as the second wiring layer in a part or the entire of the peripheral region excluding the connection region.

19. An electronic apparatus comprising the semiconductor device according to claim 18 .

20. An electronic apparatus comprising the semiconductor device according to claim 15 .

Assignees

• Seiko Epson Corp

Inventors

• Kasai Toshiyuki
• Koshihara Takeshi

Classifications

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01L23/60 Primary

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic