Semiconductor devices and structures thereof

Patent metadata

Field	Value
Publication number	US-9401322-B2
Application number	US-201113190310-A
Country	US
Kind code	B2
Filing date	Jul 25, 2011
Priority date	Jun 13, 2005
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
conductive lines disposed on a workpiece, the conductive lines having a conductive line top regions;
a porous insulating material comprising a plurality of pores disposed between a first set of the conductive lines, the porous insulating material comprising a porous insulating material top region, wherein the porous insulating material top region is adjacent the conductive line top regions;
an impermeable insulating material disposed between a second set of the conductive lines, the impermeable insulating material comprising a impermeable insulating material top region, wherein the impermeable insulating material top region is adjacent the conductive line top regions, and wherein a top surface of the porous insulating material top region, a top surface of the impermeable insulating material, and top surfaces of the conductive line top regions are coplanar;
a space comprising air gaps disposed between the conductive lines and beneath the porous insulating material;
a metal cap layer directly disposed on the conductive lines; and
an insulating cap layer directly disposed on the porous insulating material and the metal cap layer.

2. The semiconductor device according to claim 1 , wherein the insulating cap layer comprises SiCN or SiN.

3. The semiconductor device according to claim 1 , wherein the metal cap layer comprises CoW, CoWP, or TaN.

4. The semiconductor device according to claim 1 , further comprising a barrier layer disposed over sidewalls of the conductive lines.

5. The semiconductor device according to claim 1 , wherein the space further comprises an insulating material.

6. The semiconductor device according to claim 5 , wherein the insulating material comprises polynorbornene, non-photosensitive chemicals (NFC), or other organic polymers.

7. The semiconductor device according to claim 5 , wherein the insulating material comprises a carbonaceous material.

8. The semiconductor device according to claim 1 , wherein the porous insulating material comprises a carbon-free material.

9. The semiconductor device according to claim 1 , wherein the porous insulating material comprises a siloxane-organic co-polymer with an Si content of about 10%-20%.

10. The semiconductor device according to claim 1 , wherein the insulating cap layer comprises about 500 Angstroms or less of SiCN or SiN, and wherein the metal cap layer comprises about 200 Angstroms or less of CoW, CoWP, or TaN.

11. A semiconductor device, comprising:
conductive lines disposed on a workpiece;
a porous insulating material disposed between a first set of the conductive lines;
an impermeable insulating material disposed between a second set of the conductive lines, wherein the porous insulating material, the impermeable insulating material share a coplanar top surface;
a space comprising air gaps disposed between the conductive lines and beneath the porous insulating material;
a first cap layer directly disposed on the conductive lines, wherein the first cap layer comprises CoW, CoWP, or TaN; and
a second cap layer directly disposed on the porous insulating material and the first cap layer, wherein the second cap layer comprises SiCN or SiN.

12. The semiconductor device according to claim 11 , wherein the porous insulating material comprises a first thickness, wherein the space comprise a second thickness, wherein the conductive lines comprise a third thickness, wherein the first thickness comprises about 25% to 34% of the third thickness, and wherein the second thickness comprises about 66% to 75% of the third thickness.

13. The semiconductor device according to claim 11 , wherein the space further comprises an insulating material.

14. The semiconductor device according to claim 11 , wherein the first cap layer comprises about 200 Angstroms or less.

15. The semiconductor device according to claim 14 , wherein the second cap layer comprises about 500 Angstroms or less.

16. A semiconductor device, comprising:
first conductive lines disposed on a workpiece in a memory array region;
second conductive lines disposed on the workpiece in a peripheral region or a support region;
a first insulating material disposed between the first conductive lines;
a first cap layer disposed over the first insulating material;
a second insulating material disposed between the second conductive lines, wherein the first insulating material is permeable between the first conductive lines, wherein the second insulating material is impermeable between the second conductive lines, and wherein the first insulating material, the second insulating material, the first conductive lines and the second conductive lines are coplanar;
a third insulating material disposed beneath the first insulating material between the second conductive lines; and
air gaps disposed beneath the first insulating material between the first conductive lines but not between the second conductive lines.

17. The semiconductor device according to claim 16 , wherein the first cap layer comprises about 500 Angstroms or less of SiCN or SiN.

18. The semiconductor device according to claim 16 , further comprising a second cap layer disposed over the first conductive lines, wherein the second cap layer comprises about 200 Angstroms or less of CoW, CoWP, or TaN.

19. The semiconductor device according to claim 16 , wherein a thickness of the first insulating material comprises 25% to 34% of a thickness of a first conductive line and wherein a thickness of the air gaps comprises 66% to 75% of the thickness of the first conductive line.

20. A semiconductor device, comprising:
first conductive lines disposed on a workpiece in a first region;
second conductive lines disposed on the workpiece in a second region, wherein the distance between the second conductive lines in the second region is different from the distance between the first conductive lines in the first region;
a first insulating material disposed between the first conductive lines;
a first cap layer disposed over the first insulating material;
a second insulating material disposed between the second conductive lines, wherein the first insulating material is permeable between the first conductive lines and the second insulating material is impermeable between the second conductive lines, and wherein the first insulating material, the second insulating material, the first conductive lines and the second conductive lines are coplanar;
a third insulating material disposed beneath the first insulating material between the second conductive lines; and
air gaps disposed beneath the first insulating material between the first conductive lines but not between the second conductive lines.

21. The semiconductor device according to claim 20 , wherein the first cap layer comprises SiCN or SiN.

22. The semiconductor device according to claim 20 , further comprising a second cap layer disposed over the first conductive lines, wherein the second cap layer comprises CoW, CoWP, or TaN.

23. The semiconductor device according to claim 22 , wherein the first cap layer comprises about 500 Angstroms or less, and wherein the second cap layer comprises about 200 Angstroms or less.

24. The semiconductor device according to claim 20 , wherein a thickness of the first insulating material comprises 25% to 34% of a thickness of a first conductive line and wherein a thickness of the air gaps comprises 66% to 75% of the thickness o

Assignees

• Naujok Markus
• Wendt Hermann
• Gutmann Alois
• Pallachalil Muhammed Shafi
• Infineon Technologies Ag

Inventors

• Naujok Markus
• Wendt Hermann
• Gutmann Alois
• Pallachalil Muhammed Shafi

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/495 Primary

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H01L21/7682

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic