Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

Patent metadata

Field	Value
Publication number	US-9401206-B2
Application number	US-201514680268-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Oct 13, 2011
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

First claim

That which is claimed is:

1. A semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and
a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said floating body upon transfer thereto;
wherein said floating body has a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said memory cell further comprising first and second regions at first and second locations of said memory cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
wherein said transfer is performed to said at least two of said memory cells in parallel.

2. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

3. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element is electrically connected to said capacitorless transistor and a distance between said bipolar resistive change element and said capacitorless transistor, when electrically connected, is in the range from about 90 nm to 1 μm.

4. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

5. The semiconductor memory array of claim 4 , wherein said bipolar resistive change element is electrically connected to said one of said first and second regions via a conductive element.

6. The semiconductor memory array of claim 4 , further comprising an addressable line electrically connected to said bipolar resistive change element.

7. The semiconductor memory array of claim 6 , wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.

8. The semiconductor memory array of claim 1 , further comprising:
a substrate being made of a material having said second conductivity type; and
a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;
wherein said floating body of each said memory cell is formed between said first and second regions and said buried layer; and
wherein said non-volatile memory is electrically connected to one of said first and second regions.

9. The semiconductor memory array of claim 1 , further comprising:
a substrate being made of a material having said second conductivity type;
a well in said substrate, said well having said first conductivity type; and
a buried layer located between said well and said first and second regions, spaced apart from said first and second regions and having said second conductivity type;
wherein said floating body of each said memory cell is formed between said first and second regions and said buried layer;
and wherein said non-volatile memory is electrically connected to one of said first and second regions.

10. An integrated circuit comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and
a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said floating body upon transfer thereto;
wherein said floating body has a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said memory cell further comprising first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
a circuitry to perform said transfer.

11. The integrated circuit of claim 10 , wherein said transfer is performed to said at least two of said memory cells in parallel.

12. The semiconductor memory array of claim 10 , wherein said resistance change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

13. The semiconductor memory array of claim 10 , wherein said bipolar resistive change element is electrically connected to said capacitorless transistor and a distance between said bipolar resistive change element and said capacitorless transistor, when electrically connected, is in the range of from about 90 nm to 1 μm.

14. The semiconductor memory array of claim 10 , wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

15. A semiconductor memory cell comprising:
a bipolar device configured to store data when power is applied to said cell; and
a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said bipolar device upon transfer thereto.

16. The semiconductor memory cell of claim 15 , wherein said bipolar resistive change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

17. The semiconductor memory cell of claim 15 , wherein said bipolar resistive change element is electrically connected to said bipolar device and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range of from about 90 nm to 1 μm.

18. The semiconductor memory cell of claim 15 , wherein said bipolar device comprises a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said memory cell further comprising first and second regions at first and second locations of said memory cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

19. The semiconductor memory cell of claim 18 , wherein said bipolar resistive change element is electrically connected to said one of said first and second regions via a conductive element.

20. The semiconductor memory cell of claim 15 , further comprising an addressable line electrically connected to said bipolar resistive change element.

Assignees

• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto

Classifications

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C14/00

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title