System and method for efficient buffer management for banked shared memory designs

Patent metadata

Field	Value
Publication number	US-9400606-B2
Application number	US-201514816762-A
Country	US
Kind code	B2
Filing date	Aug 3, 2015
Priority date	May 31, 2013
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A system and method for efficient buffer management for banked shared memory designs are provided. In one embodiment, a controller within the switch is configured to manage the buffering of the shared memory banks by allocating full address sets to write sources. Each full address set that is allocated to a write source includes a number of memory addresses, wherein each memory address is associated with a different shared memory bank. A size of the full address set can be based on a determined number of buffer access contenders.

First claim

What is claimed is:

1. A switch, comprising:
a plurality of shared memory banks configured for access by a first number of first sources and a second number of second sources; and
a controller configured to allocate full address sets to one of the first number of first sources, wherein each full address set includes a third number of memory addresses, each memory address in the third number of memory addresses being associated with a different shared memory bank, the third number being at least as large as the first number,
wherein the one of the first number of first sources selects one of the memory addresses from a full address set when accessing to a shared memory bank.

2. The switch of claim 1 , further comprising the controller being configured to monitor a fourth number of full address sets available to a source among the first sources, and to generate a flow control message in response to the monitoring.

3. The switch of claim 1 , wherein a number of the full address sets allocated to the one of the first number of first sources is determined using a number of packets handled by the one of the first number of first sources.

4. The switch of claim 1 , wherein the first sources comprise write sources and the second sources comprise read sources, and wherein the accessing to the shared memory bank comprises writing a packet to the shared memory bank.

5. The switch of claim 4 , wherein the controller implements a write first policy.

6. The switch of claim 4 , wherein the controller implements a read first policy.

7. The switch of claim 1 , wherein the third number is equal to the first number.

8. The switch of claim 1 , wherein the third number is equal to the first number plus the second number.

9. A method, comprising:
allocating full address sets to one of a first number of sources accessing a plurality of shared memory banks, each full address set comprising a second number of memory addresses, each memory address in the second number of memory addresses being associated with a different shared memory bank, wherein the second number is determined using the first number;
selecting one of the memory addresses from a full address set among the allocated full address sets; and
accessing a shared memory bank at the selected memory address from the one of the first number of sources, wherein the accessing to the shared memory bank at the selected memory address removes a status of the address set containing the selected memory address as a full address set.

10. The method of claim 9 , further comprising:
a third number of read sources reading packets from the plurality of shared memory banks,
wherein the first number of sources comprises write sources writing packets to the plurality of shared memory banks, and
wherein the accessing to the shared memory bank at the selected memory address comprises writing a packet to the shared memory bank at the selected memory address.

11. The method of claim 10 , wherein the second number is equal to the first number plus the third number.

12. The method of claim 9 , further comprising:
monitoring a fourth number of full address sets available to a first source among the sources; and
generating a flow control message in response to the monitoring.

13. The method of claim 11 , wherein the monitoring comprises comparing the fourth number to a threshold value.

14. The method of claim 9 , wherein the second number is equal to or bigger than the first number.

15. The method of claim 9 , further comprising:
changing, after the accessing, a designation of the address set containing the selected memory address from a full address set to a partial address set.

16. A non-transitory computer-readable medium having machine instructions stored therein, the instructions when executed by at least one processor, causing the at least one processor to perform operations comprising:
allocating full address sets to one of a first number of sources accessing to a plurality of shared memory banks, each full address set comprising a second number of memory addresses, each memory address in the second number of memory addresses being associated with a different shared memory bank, wherein the second number is determined using the first number;
selecting one of the memory addresses from a full address set among the allocated full address sets;
causing the one of the first number of sources to access a shared memory bank at the selected memory address; and
reducing a number of the full address sets that are available to the one of the first number of sources in response to accessing the shard memory bank at the selected memory address.

17. The non-transitory computer-readable medium of claim 16 , wherein the instructions when executed by the at least one processor, causing the at least one processor to perform operations further comprising:
monitoring the number of the full address sets available to a first source among the sources; and
generating a flow control message in response to the monitoring.

18. The non-transitory computer-readable medium of claim 16 ,
wherein the first number of sources comprises write sources writing packets to the plurality of shared memory banks, and
wherein the accessing to the shared memory bank at the selected memory address comprises writing a packet to the shared memory bank at the selected memory address.

19. The non-transitory computer-readable medium of claim 16 ,
wherein the first number of sources comprises read sources reading packets from the plurality of shared memory banks, and
wherein the accessing to the shared memory bank at the selected memory address comprises reading a packet from the shared memory bank at the selected memory address.

20. The non-transitory computer-readable medium of claim 16 , wherein the second number is equal to or bigger than the first number.

Assignees

• Broadcom Corp

Inventors

• Matthews William Brad

Classifications

• H04L49/90 Primary

  Buffering arrangements · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title