Pluggable transceiver module with enhanced circuitry

Patent metadata

Field	Value
Publication number	US-9397753-B2
Application number	US-201213421666-A
Country	US
Kind code	B2
Filing date	Mar 15, 2012
Priority date	Sep 15, 2009
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

First claim

The invention claimed is:

1. A pluggable transceiver comprising:
a receive section including:
receive digital function circuitry;
a line decoder circuit having an input and having an output connected to said receive digital function circuitry; and
a line encoder circuit having an input connected to the said receive digital function circuitry and having an output;

a transmit section including:
transmit digital function circuitry;
a line decoder circuit having an input and having an output connected to said transmit digital function circuitry; and
a line encoder circuit having an input connected to said transmit digital function circuitry and having an output; and

a controller having a control communication interface and connected to said receive section and said transmit section,
wherein said controller controls and said receive and transmit digital function circuitry.

2. The pluggable transceiver of claim 1 ,
wherein said receive section further includes:
a receive amplifier having an input coupled to a received signal and having an output digital signal connected to said line decoder circuit input; and
a balanced output driver having an input connected to said line encoder circuit output and having an output which provides a balanced digital output signal;

wherein said transmit section further includes:
a balanced input buffer having an input to receive a balanced digital signal and having an output digital signal connected to said line decoder circuit input; and
a transmit amplifier having an input connected to said line encoder circuit output and having an output signal coupled to a transceiver output signal; and

wherein said controller controls said receive and transmit amplifiers.

3. The pluggable transceiver of claim 2 , wherein said receive digital function circuitry includes receive bit error rate circuitry for monitoring bit error rates and said transmit digital function transmit bit error rate circuitry monitors bit error rates.

4. The pluggable transceiver of claim 3 ,
wherein said receive digital circuitry section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output connected to said receive bit error rate circuitry; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input; and

wherein said transmit section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output connected to said transmit bit error rate circuitry; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input.

5. The pluggable transceiver of claim 4 ,
wherein said receive bit error rate circuitry is further connected to said input of said forward error correction decoder and said output of said forward error correction encoder, and
wherein said transmit bit error rate circuitry is further connected to said input of said forward error correction decoder and said output of said forward error correction encoder.

6. The pluggable transceiver of claim 3 ,
wherein said receive digital circuitry section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input,
wherein said receive bit error rate circuitry is connected to said input of said forward error correction decoder and said output of said forward error correction encoder, and

wherein said transmit section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input,
wherein said transmit bit error rate circuitry is connected to said input of said forward error correction decoder and said output of said forward error correction encoder.

7. The pluggable transceiver of claim 2 ,
wherein said receive section further includes:
a photo-detector which provides an output electrical signal based on a received optical signal to said input of said receive amplifier; and

wherein the transmit section further includes:
a laser diode connected to said transmit amplifier output signal and providing an optical output signal.

8. A network device comprising:
a pluggable transceiver including:
a receive section including:
receive digital function circuitry;
a line decoder circuit having an input and having an output connected to said receive digital function circuitry; and
a line encoder circuit having an input connected to the said receive digital function circuitry and having an output;

a transmit section including:
transmit digital function circuitry;
a line decoder circuit having an input and having an output connected to said transmit digital function circuitry; and
a line encoder circuit having an input connected to said transmit digital function circuitry and having an output; and

a controller having a control communication interface and connected to said receive section and said transmit section, wherein said controller controls said receive and transmit digital function circuitry;

a processor coupled to said pluggable transceiver; and
a network data transfer circuit coupled to said pluggable transceiver.

9. The network device of claim 8 ,
wherein said receive section further includes:
a receive amplifier having an input coupled to a received signal and having an output digital signal connected to said line decoder circuit input; and
a balanced output driver having an input connected to said line encoder circuit output and having an output which provides a balanced digital output signal;

wherein said transmit section further includes:
a balanced input buffer having an input to receive a balanced digital signal and having an output digital signal connected to said line decoder circuit input; and
a transmit amplifier having an input connected to said line encoder circuit output and having an output signal coupled to a transceiver output signal; and

wherein said controller controls said receive and transmit amplifiers.

10. The network device of claim 9 , wherein said receive digital function circuitry includes receive bit error rate circuitry for monitoring bit error rates and said transmit digital function transmit bit error rate circuitry monitors bit error rates.

11. The network device of claim 10 ,
wherein said receive digital circuitry section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output connected to said receive bit error rate circuitry; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input; and

wherein said transmit section further includes:
a forward error correction decoder having an input coupled to said line decoder circuit output and having an output connected to said transmit bit error rate circuitry; and
a forward error detection encoder having an input coupled to said forward error correction decoder output and having an output coupled to said line encoder circuit input.

Assignees

• Skirmont David Aaron
• Kilkenny Daniel Kiernan
• Varanasi Surya Parkash
• Ko Kung-Ling
• Brocade Comm Systems Inc

Inventors

• Skirmont David Aaron
• Kilkenny Daniel Kiernan
• Varanasi Surya Parkash
• Ko Kung-Ling

Classifications

• H04L2209/34

  Encoding or coding, e.g. Huffman coding or error correction · CPC title

• H04L1/203

  Details of error rate determination, e.g. BER, FER or WER · CPC title

• H04L1/004

  by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00) · CPC title

• H04L9/065

  Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3 · CPC title

• H04B10/40 Primary

  Transceivers · CPC title