Adaptive read error recovery for memory devices

Patent metadata

Field	Value
Publication number	US-9397703-B2
Application number	US-201314096752-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Dec 4, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.

First claim

What is claimed is:

1. A method, comprising:
detecting an error of a solid state memory device in response to a determination that a read to the memory failed;
determining whether a counter value is above a predetermined value;
if it is determined that the counter value is above the predetermined value:
determining that the error is a catastrophic error; and
bypassing a voltage error recovery process configured to adjust the threshold voltage used to access the memory; and

if it is determined that the counter value is not above the predetermined value:
determining if a threshold voltage used to access the memory has been shifted;
if it is determined that the threshold voltage used to access the memory has been shifted:
determining a direction of the threshold voltage; and
initiating a type of voltage error recovery process based on the direction of the voltage shift.

2. The method of claim 1 , wherein if it is determined that the error is the catastrophic error, performing a redundant parity recovery process.

3. The method of claim 2 , wherein the redundant parity recovery process is an outer code parity process having an outer code and the outer code is a low-density parity check (LDPC) code.

4. The method of claim 2 , wherein the redundant parity recovery process is an outer code parity process having an outer code and the outer code is a Reed Solomon code.

5. The method of claim 1 , wherein detecting the error of the memory device comprises detecting the error of the memory device by determining that a codeword did not converge.

6. The method of claim 1 , wherein the error is detected in response to a decoder not detecting convergence.

7. The method of claim 6 , wherein the decoder is a low-density parity check (LDPC) decoder.

8. The method of claim 1 , wherein a decoder determines an XOR associated with each parity bit in a codeword and the codeword does not converge if at least one XOR results in a value of 1.

9. The method of claim 8 , wherein the counter value is the number of parity bits in which the associated XOR results in a value of 1.

10. A method, comprising:
detecting an error of a solid state memory device in response to a determination that a read to the memory failed;
determining whether a counter value is above a predetermined value;
if it is determined that the counter value is above the predetermined value:
determining that the error is a catastrophic error;
bypassing a voltage error recovery process, the voltage error recovery process configured to adjust the threshold voltage used to access the memory; and
performing a redundant parity recovery process;

if it is determined that the counter value is not above the predetermined value:
determining if a threshold voltage used to access the memory has been shifted;
if it is determined that the threshold voltage used to access the memory has been shifted:
determining a direction of the threshold voltage shift; and
initiating a type of voltage error recovery process based on the direction of the voltage shift.

11. An apparatus comprising:
a controller capable of being coupled to a solid state memory, the controller configured to perform:
detecting an error of the memory based on a determination that a read to the memory failed;
determining whether a counter value is above a predetermined value;
if it is determined that the counter value is above the predetermined value:
determining that the error is a catastrophic error; and
bypassing a voltage error recovery process, the voltage error recovery process configured to adjust the threshold voltage used to access the memory;

if it is determined that the counter value is not above the predetermined value:
determining if a threshold voltage used to access the memory has been shifted;
if it is determined that the threshold voltage used to access the memory has been shifted:
determining a direction of the threshold voltage shift; and

initiating a type of voltage error recovery process based on the direction of the voltage shift.

12. The apparatus of claim 11 wherein if it is determined that the error is the catastrophic error, the controller is configured to perform a redundant parity recovery process.

13. The apparatus of claim 12 , wherein the redundant parity recovery process is an outer code parity process having an outer code and the outer code is a low-density parity check (LDPC) code.

14. The apparatus of claim 12 , wherein the redundant parity recovery process is an outer code parity process having an outer code and the outer code is a Reed Solomon code.

15. The apparatus of claim 11 , wherein the controller is configured to detect an error of the memory device by determining that a codeword did not converge.

16. The apparatus of claim 11 , wherein the controller is configured to detect the error in response a decoder not detecting convergence.

17. The apparatus of claim 16 , wherein the decoder is a low-density parity check (LDPC) decoder.

18. The apparatus of claim 11 , wherein initiating a type of voltage error recovery process based on the direction of the voltage shift further comprises:
initiating an endurance loss recovery process if it is determined that voltage shift was positive; and
initiating a retention loss recovery process if it is determined that the voltage shift was negative.

19. The apparatus of claim 11 , wherein if it is determined that the threshold voltage used to access the memory has not been shifted, initiating an interference cancellation recovery process.

Assignees

• Seagate Technology Llc

Inventors

• Ghaly Mai A
• Patapoutian Ara

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• H03M13/17 Primary

  Burst error correction, e.g. error trapping, Fire codes · CPC title

• G06F11/141

  for bus or memory accesses · CPC title

• G11B2020/185

  using an low density parity check [LDPC] code · CPC title