Voltage regulator, voltage regulating system, memory chip, and memory device
US-9188999-B2 · Nov 17, 2015 · US
US9397653B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9397653-B2 |
| Application number | US-201414465387-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2014 |
| Priority date | Feb 13, 2014 |
| Publication date | Jul 19, 2016 |
| Grant date | Jul 19, 2016 |
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According to one embodiment, the semiconductor device includes a power-on reset circuit and a constant voltage generation circuit. The power-on reset circuit generates a power-on reset signal to initialize an internal circuit when power supply is turned on. The constant voltage generation circuit supplies an output voltage to the internal circuit. The constant voltage generation circuit includes a differential amplifier, a first MOS transistor, a second MOS transistor, a switch, and a pull-up unit. The pull-up unit is provided between the power supply input terminal and the gate terminal of the second MOS transistor. The pull-up unit controls a voltage applied to the gate terminal of the second MOS transistor in accordance with the power-on reset signal.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a power-on reset circuit to generate a power-on reset signal to initialize an internal circuit when a power supply is turned on; and a constant voltage generation circuit to supply an output voltage to the internal circuit, wherein the constant voltage generation circuit includes a differential amplifier, a first MOS transistor, a second MOS transistor, a switch, and a pull-up unit, the differential amplifier outputs a voltage depending upon a difference between a reference voltage and a feedback voltage obtained by dividing the output voltage, the first MOS transistor has a first terminal connected to a power supply input terminal supplied with a power supply voltage provided by the power supply, a second terminal connected to an output terminal to output the output voltage, and a gate terminal connected to an output side of the differential amplifier, the second MOS transistor has a first terminal connected to the power supply input terminal and a second terminal connected to the output terminal, the second MOS transistor is connected in parallel with the first MOS transistor, the switch is provided between the output side of the differential amplifier and a gate terminal of the second MOS transistor to control opening/closing between the output side of the differential amplifier and the gate terminal of the second MOS transistor in accordance with the power-on reset signal, and the pull-up unit is provided between the power supply input terminal and the gate terminal of the second MOS transistor to control a voltage applied to the gate terminal of the second MOS transistor in accordance with the power-on reset signal. 2. The semiconductor device according to claim 1 , wherein when the constant voltage generation circuit is in a reset state brought about by the power-on reset signal, the switch disconnects a path between the output side of the differential amplifier and the gate terminal of the second MOS transistor, and the pull-up unit applies a voltage of a pull-up level to the gate terminal of the second MOS transistor, and when the reset state in the constant voltage generation circuit brought about by the power-on reset signal is canceled, the switch connects the path between the output side of the differential amplifier and the gate terminal of the second MOS transistor, and an output from the pull-up unit to the gate terminal of the second MOS transistor is stopped. 3. The semiconductor device according to claim 1 , wherein the pull-up unit comprises: a third MOS transistor having a first terminal connected to the power supply input terminal and a gate terminal supplied with the power-on reset signal as an input; and a fourth MOS transistor having a first terminal connected to a second terminal of the third MOS transistor and a gate terminal connected to a second terminal of the fourth MOS transistor and the gate terminal of the second MOS transistor. 4. The semiconductor device according to claim 3 , wherein when the power-on reset signal is at a “low” level, the third MOS transistor turns on, and when the power-on reset signal is at a “high” level, the third MOS transistor turns off. 5. The semiconductor device according to claim 4 , wherein the first to fourth MOS transistors are P-channel MOS transistors. 6. The semiconductor device according to claim 1 , wherein the power-on reset circuit and the constant voltage generation circuit are provided in same semiconductor integrated circuit. 7. The semiconductor device according to claim 1 , wherein the pull-up unit includes a third MOS transistor, the third MOS transistor has a first terminal connected to the power supply input terminal, a second terminal connected to the gate terminal of the second MOS transistor, and a gate terminal supplied with the power-on reset signal as an input. 8. The semiconductor device according to claim 7 , wherein when the power-on reset signal is at a “low” level, the third MOS transistor turns on, and when the power-on reset signal is at a “high” level, the third MOS transistor turns off. 9. The semiconductor device according to claim 8 , wherein the first to third MOS transistors are P-channel MOS transistors. 10. The semiconductor device according to claim 1 , wherein the switch is any of an N-channel MOS transistor and a transfer gate. 11. The semiconductor device according to claim 1 , wherein the semiconductor device is applied to a mobile terminal, a digital camera, a notebook personal computer, or a mobile electronic device.
in field-effect transistor switches · CPC title
Power supply means, e.g. regulation thereof (for memories G11C) · CPC title
sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title
using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title
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