Delay circuit

Patent metadata

Field	Value
Publication number	US-9397646-B2
Application number	US-201414489055-A
Country	US
Kind code	B2
Filing date	Sep 17, 2014
Priority date	Sep 17, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

First claim

What is claimed is:

1. A delay circuit, comprising:
a first delay path having an input coupled to an input of the delay circuit, and an output wherein the first delay path comprises a first plurality of delay gates coupled in series;
a second delay path having an input coupled to the input of the delay circuit, and an output, wherein the second delay path comprises a second plurality of delay gates coupled in series;
a plurality of switches, wherein each switch is coupled between an output of a different one of the first plurality of delay gates and an output of a different one of the second plurality of delay gates, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals; and
a multiplexer having a first input coupled to the output of the first delay path, a second input coupled to the output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

2. The delay circuit of claim 1 , wherein each of the first plurality of delay gates comprises a NAND gate.

3. The delay circuit of claim 2 , wherein each NAND has a first input coupled to a supply voltage and a second input coupled to a signal path of a signal being delayed by the first delay path.

4. The delay circuit of claim 1 , wherein each of the first plurality of delay gates comprises an inverter.

5. The delay circuit of claim 1 , wherein the first delay path comprises a plurality of capacitors, and each of the capacitors is coupled to the output of a different one of the first plurality of delay gates.

6. The delay circuit of claim 1 , further comprising a delay controller, wherein the delay controller is configured to control the plurality of switches using the plurality of select signals and to control the multiplexer using the second select signal, and to set the delay circuit to one of a plurality of different delay settings, each delay setting corresponding to a different combination of values for the plurality of select signals and the second select signal.

7. The delay circuit of claim 6 , wherein a first one of the delay settings corresponds to one of the plurality of switches turned on with first remaining ones of the plurality of switches turned off, and selection of the first delay path by the multiplexer.

8. The delay circuit of claim 7 , wherein a second one of the delay settings corresponds to two of the plurality of switches turned on with second remaining ones of the plurality of switches turned off, and the selection of the first delay path by the multiplexer.

9. The delay circuit of claim 8 , wherein a third one of the delay settings corresponds to three of the plurality of switches turned on with third remaining ones of the plurality of switches turned off, and the selection of the first delay path by the multiplexer.

10. The delay circuit of claim 7 , wherein a second one of the delay settings corresponds to all of the plurality of switches turned on, and the selection of the first delay path by the multiplexer.

11. The delay circuit of claim 7 , wherein a second one of the delay settings corresponds to the one of the plurality of switches turned on with the first remaining ones of the plurality of switches turned off, and selection of the second delay path by the multiplexer.

12. The delay circuit of claim 11 , wherein a third one of the delay settings corresponds to two of the plurality of switches turned on with second remaining ones of the plurality of switches turned off, and the selection of the second delay path by the multiplexer.

13. A method for controlling delay of a delay circuit, the delay circuit comprising first and second delay paths and a plurality of switches, wherein the first delay path comprises a first plurality of delay gates coupled in series, the second delay path comprises a second plurality of delay gates coupled in series, and each of the plurality of switches is coupled between an output of a different one of the first plurality of delay gates and an output of a different one of the second plurality of delay gates, the method comprising:
inputting a signal to be delayed to an input of the first delay path and an input of the second delay path;
selectively turning each switch on or off according to a desired one of a plurality of delay settings; and
selecting an output of the first delay path or an output of the second delay path according to the desired one of the plurality of delay settings.

14. The method of claim 13 , wherein each of the first plurality of delay gates comprises a NAND gate.

15. The method of claim 13 , wherein each of the first plurality of delay gates comprises an inverter.

16. The method of claim 13 , wherein a first one of the delay settings corresponds to one of the plurality of switches turned on with first remaining ones of the plurality of switches turned off, and selection of the output of the first delay path.

17. The method of claim 16 , wherein a second one of the delay settings corresponds to two of the plurality of switches turned on with second remaining ones of the plurality of switches turned off, and the selection of the output of the first delay path.

18. The method of claim 16 , wherein a second one of the delay settings corresponds to all of the plurality of switches turned on, and the selection of the output of the first delay path.

19. The method of claim 16 , wherein a second one of the delay settings corresponds to the one of the plurality of switches turned on with the first remaining ones of the plurality of switches turned off, and selection of the output of the second delay path.

20. The method of claim 19 , wherein a third one of the delay settings corresponds to two of the plurality of switches turned on with second remaining ones of the plurality of switches turned off, and the selection of the output of the second delay path.

21. The method of claim 13 , further comprising selecting the desired one of the plurality of the delay settings based on a skew between the signal being delayed and another signal.

22. An apparatus for controlling delay of a delay circuit, the delay circuit comprising first and second delay paths and a plurality of switches, wherein the first delay path comprises a first plurality of delay gates coupled in series, the second delay path comprises a second plurality of delay gates coupled in series, and each of the plurality of switches is coupled between an output of a different one of the first plurality of delay gates and an output of a different one of the second plurality of delay gates, the apparatus comprising:
means for inputting a signal to be delayed to an input of the first delay path and an input of the second delay path;
means for selectively turning each switch on or off according to a desired one of a plurality of delay settings; and
means for selecting an output of the first delay path or an output of the second delay path according to the desired one of the plurality of delay settings.

23. The apparatus of claim 22 , wherein a first one of the delay settings corresponds to one of the plurality of switches turned on with first remaining ones of the plurality of switches turned off, and selection of the output of the first delay path.

24. The apparatus of claim 23 , wherein a second on

Assignees

• Qualcomm Inc

Inventors

• Singh Guneet
• Cheng Yuehchun Claire
• Diffenderfer Jan Christian
• Srinivas Vaishnav
• Kim Robert Won Chol

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1066

  Output synchronization · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title